Abstract: A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communication paths and/or the I/O paths. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. Configurable signal processing logic may be configured to host one or more signal processing functions which allow data to be autonomously accessed from the processor local memories, processed, and re-deposited in a local memory.

Abstract: An image processing apparatus by which an excellent image can be obtained even after compression and expansion. A compression circuit (12) has a line scanning unit which divides original image data into color data groups in relation to respective pixels, a line compression unit (24) which expresses the value (y) of the color data corresponding to each pixel position in a predetermined section with a polynomial: y=ax3+bx2+cx+d wherein (x) denotes the pixel position which is a variable and a coefficient calculation unit (26) which obtains the color data values corresponding to the respective pixel positions in accordance with the received coefficients and pixel positions. The restored image data are outputted to a display apparatus, etc.

Abstract: A quad-processor arrangement having 6 communications paths, one path between each of every possible pair of processors. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. The communications paths are controlled and interfaced to the processors through field programmable logic, which allows the board to be configured both statically and dynamically to optimize the data transfer characteristics of the module to match the requirements of the application software. The programmable logic may be configured so that the module emulates other existing board architectures in order to support legacy applications.