Abstract: A semiconductor module a metal base plate having a semiconductor unit including a semiconductor element, the metal base plate having an upper surface and a bottom surface opposite to each other and the semiconductor element being mounted on the upper surface, and a case surrounding a periphery of the semiconductor unit and being bonded to the upper surface of the metal base plate. The case includes a first positioning portion formed by a protrusion protruding a bottom of the case toward the metal base plate, and a second positioning portion formed by a hole or a cutout so as to at least partially overlap with the first positioning portion in a plan view of the semiconductor module. The metal base plate includes a first engagement portion formed by a hole or a cutout with which the first positioning portion is engageable.

Abstract: A positive electrode circuit pattern layer and a negative electrode circuit pattern layer each have a terminal region extending in a long-side direction of a rectangular insulating plate. Thicknesses of a positive electrode bonding region of a positive electrode terminal and a negative electrode bonding region of a negative electrode terminal are respectively less than thicknesses of the terminal regions of the positive electrode circuit pattern layer and the negative electrode circuit pattern layer. The lengths in the long-side direction of the positive electrode bonding region of the positive electrode terminal and the negative electrode bonding region of the negative electrode terminal are respectively greater than or equal to half the lengths in the long-side direction of the terminal regions of the positive electrode circuit pattern layer and negative electrode circuit pattern layer.

Abstract: A semiconductor device, having: a substrate having a main surface with a recess; a device structure at the main surface; an interlayer insulating film covering the device structure; a contact hole penetrating through the interlayer insulating film to expose a portion of the device structure, the contact hole having a bottom configured by the recess; a barrier metal, including a titanium film provided along the side wall of the contact hole, and a titanium nitride film stacked on the titanium film and formed at the bottom of the contact hole; a titanium silicide film provided along an inner wall of the recess; a tungsten film provided on the barrier metal; and a metal electrode provided on the interlayer insulating film and the tungsten film. An upper surface of the titanium nitride film on the bottom of the contact hole is closer to the metal electrode than is the main surface.

Abstract: A highly sensitive and highly durable positive charging multilayer electrophotographic photoreceptor includes: a conductive substrate; a charge transport layer containing at least a first hole transport material and a first resin binder; and a charge generation layer containing at least a second hole transport material, an electron transport material, a charge generation material, and a second resin binder, the charge transport layer and the charge generation layer being sequentially laminated on the conductive substrate.

Abstract: External connection reliability is improved with an external connector including an external connection terminal, and a nut provided on a bottom surface side of the external connection terminal. The external connection terminal has a conductor, a first metal layer provided on an upper surface of the conductor, a second metal layer provided on the first metal layer, and a bottom surface metal layer provided on a bottom surface of the conductor.

Abstract: An integrated circuit configured to switch a transistor in a power supply circuit. The integrated circuit includes a first terminal to which a first resistor is coupled; a first detection circuit configured to detect whether a load of the power supply circuit is in an overload state; a second detection circuit configured to detect whether a current flowing through the transistor is overcurrent; an oscillator circuit configured to output an oscillator signal with a cycle corresponding to a first resistance value of the first resistor; and a driving signal output circuit configured to output a driving signal to turn on the transistor, based on the oscillator signal, and turn off the transistor, based on a feedback voltage corresponding to the output voltage. The driving signal output circuit further outputs the driving signal to turn off the transistor, in response to the current flowing through the transistor reaching overcurrent.

Abstract: There is provided a semiconductor device including: a semiconductor substrate that has an upper surface and a lower surface and that is provided with a drift region of a first conductivity type; a trench portion that is provided to reach the drift region from the upper surface of the semiconductor substrate; and a mesa portion that is interposed between trench portions, in which the mesa portion has a base region of a second conductivity type that is provided between the drift region and the upper surface, and a first region that has a concentration peak of a hydrogen chemical concentration at a first depth position in the mesa portion.

Abstract: A cooler includes a top plate having a plurality of fins provided on a surface thereof, and a circumferential wall part provided so as to surround outer circumferences of the plurality of fins along outer circumferential edges of the top plate, and a bottom plate bonded to distal ends of the circumferential wall part and the plurality of fins. A flow path for a coolant is formed by a space enclosed by the top plate, the circumferential wall part and the bottom plate. The bottom plate has inlet and discharge portions for the coolant. The inlet and discharge portions are disposed so as to face each other diagonally with the plurality fins interposed therebetween. An inner surface of the circumferential wall part has a step part that tilts from the inner surface of the circumferential wall part toward the discharge portion at a position neighboring to the discharge portion.

Abstract: One object is to provide a semiconductor device capable of reducing loss during turn-on and degradation of forward voltage. A vertical MOSFET includes a semiconductor substrate 2 of a first conductivity type, a first semiconductor layer 1 of the first conductivity type, a second semiconductor layer 16 of a second conductivity type, first semiconductor regions 17 of the first conductivity type, first trenches 31 and a second trench 32, gate electrodes 20 provided in the first trenches 31 via a gate insulating film 19, and a Schottky electrode 29 provided in the second trench 32. The first trenches 31 are provided in a striped pattern, in a plan view and the second trench 32 surrounds the first trenches 31.

Abstract: A semiconductor device has a resistance element including a metal block, a resin layer disposed on the metal block, and a resistance film disposed on the resin layer and an insulated circuit board including an insulating plate and a circuit pattern disposed on the insulating plate and having a bonding area on a front surface thereof to which a back surface of the metal block of the resistance element is bonded. The area of the circuit pattern is larger in plan view than that of a front surface of the resistance element. The metal block has a thickness greater than that of the circuit pattern in a direction orthogonal to the back surface of the metal block. As a result, the metal block properly conducts heat generated by the resistance film of the resistance element to the circuit pattern.

Abstract: A semiconductor device includes: a first semiconductor chip and a second semiconductor chip each including a first main electrode on a bottom surface side and a second main electrode on a top surface side; a conductive member provided to electrically connect the first main electrode of the first semiconductor chip to the second main electrode of the second semiconductor chip; a first external terminal electrically connected to the second main electrode of the first semiconductor chip and partly opposed to the conductive member, and a resin member provided to be at least partly arranged between the conductive member and the first external terminal.

Abstract: A semiconductor device includes: a conductive substrate; a plurality of semiconductor chips each having a first main electrode on a bottom surface side and a second main electrode on a top surface side, the plural semiconductor chips being arranged to form a first column and a second column connected parallel to each other on the conductive substrate; and a control wiring substrate including an insulating layer, a plurality of top-surface conductive layers provided on a top surface of the insulating layer, and a plurality of bottom-surface conductive layers each having a narrower width than the insulating layer and provided on a bottom surface of the insulating layer, the bottom-surface conductive layers being arranged on the conductive substrate between the first column and the second column of the semiconductor chips.

Abstract: A semiconductor device includes an active region as a region through which main current flows, an active region perimeter that surrounds the active region, and an edge termination region that surrounds the active region perimeter. The active region perimeter includes: a semiconductor substrate; a drift layer of a first conductivity type; a base region of a second conductivity type provided on an upper surface side of the drift layer; a source region of a first conductivity type selectively provided on an upper surface side of the base region; a perimeter trench including a contact region of the second conductivity type selectively provided, having at least a sidewall on the active region side in contact with the source region, and provided to pass through the base region; and a source ring region provided to be in contact with the contact region.

Abstract: A semiconductor device includes: a drift layer; a base region provided on the drift layer; a main region provided on the drift layer; a gate electrode provided on the drift layer and buried in a gate trench extending in one direction across both ends of an active part with a gate insulating film interposed; a gate runner provided on an outer circumferential side of the active part so as to be electrically connected to the gate electrode; a gate pad provided on an inner side of the gate runner; and a resistance layer provided on the drift layer and buried in a trench for resistance extending in the one direction across the both ends of the active part with an insulating film interposed so as to be electrically connected between the gate pad and the gate runner.

Abstract: Provided is a test method comprising: preparing a plurality of groups for setting, each of which has a plurality of semiconductor devices for setting, and assigning an inspection voltage to each of the respective plurality of groups for setting; performing first testing by applying the assigned inspection voltage to the semiconductor devices for setting, and testing, at a first temperature, the plurality of semiconductor devices for setting included in each of the plurality of groups for setting; performing second testing by testing, at a second temperature different from the first temperature, a semiconductor device for setting having been determined as being non-defective and by detecting a breakdown voltage at which the semiconductor device for setting is broken; acquiring a relationship between the inspection voltage and the breakdown voltage; and setting an applied voltage used when testing a semiconductor device under test at the first temperature, based on the acquired relationship.

Abstract: Provided is a semiconductor device including a buffer region. Provided is a semiconductor device including: semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type provided in the semiconductor substrate; and a buffer region of the first conductivity type provided in the drift layer, the buffer region having a plurality of peaks of a doping concentration, wherein the buffer region has: a first peak which has a predetermined doping concentration, and is provided the closest to a back surface of the semiconductor substrate among the plurality of peaks; and a high-concentration peak which has a higher doping concentration than the first peak, and is provided closer to an upper surface of the semiconductor substrate than the first peak is.

Abstract: A semiconductor device includes a semiconductor element, a substrate including an insulating board, and first conductive plate and second conductive plate on the insulating board, and a wiring unit including a first lead frame electrically connected to the first conductive plate and having a first wiring portion wired parallel to the insulating board, a second lead frame electrically connected to the second conductive plate, and having a second wiring portion above the first lead frame and overlapping the first wiring portion in a plan view at a superimposed area, a gap between the first and second lead frames being formed in the superimposed area, and a wiring holding portion holding the first and second lead frames. The wiring holding portion includes a wiring gap portion which fills in the gap, and a wiring surface portion disposed over the second wiring portion in the superimposed area.

Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.

Abstract: An apparatus includes a base having a stage region at a front side thereof, and a plurality of suction holes in the stage region; an elastic member provided in the stage region and having a plurality of through holes, each of which is disposed at a position immediately above a corresponding one suction hole when viewed from a suction direction from the front side to a rear side of the base; and a suction unit configured to apply suction for suctioning a target member to be placed in the stage region through the suction holes in the suction direction, thereby to fix the target member to the stage region by the suction via the elastic member.

Abstract: A semiconductor module includes a first semiconductor chip including a first main electrode, a second semiconductor chip including a second main electrode, and a conductive pattern. The wiring member includes a connection portion, a first portion, a second portion, and a coupling portion. The coupling portion couples the connection portion, the first portion, and the second portion to one another. A connecting protrusion is formed on a connection surface of the connection portion. A first protrusion is formed on a first connection surface of the first portion. A second protrusion is formed on a second connection surface of the first portion. The conductive pattern and the connection surface are joined to each other by a joining material. The first main electrode and the first connection surface are joined to each other by a first joining material. The second main electrode and the second connection surface are joined to each other by a second joining material.