Abstract: A method for cooperative data transfer includes establishing a primary wireless connection with a primary access station. The primary wireless connection uses a primary synchronization channel that is transmitted during a first frame of a super frame. The super frame comprises a plurality of frames. The method also includes detecting a secondary synchronization channel generated by an alternate access station during a subsequent frame of the super frame. The method further includes determining whether the detected secondary synchronization channel has a signal strength greater than a threshold signal strength. The method additionally includes receiving permission to begin a cooperative data transfer operation with both the primary access station and the alternate access station.

Abstract: A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.

Abstract: A method is provided for reducing non-linear effects in an electronic circuit including an amplifier. The method may include receiving a modulated signal at an input of the amplifier, the modulated signal comprising a baseband signal modulated by an oscillator frequency. The method may further include substantially attenuating counter-intermodulation in the modulated signal caused by harmonics of the oscillator frequency and the baseband signal by a resonant circuit. In some embodiments, the resonant circuit may include at least one inductive element and one capacitive element coupled to the at least one inductive element, the at least one inductive element and the at least one capacitive element configured to substantially attenuate counter-intermodulation in the modulated signal.

Abstract: A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element.

Abstract: A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.

Abstract: A semiconductor device includes a capacitor provided above a substrate including electrodes and a ferroelectric film provided therebetween, a pad electrode electrically connected to one of the electrodes of the capacitor, the pad electrode being formed above the substrate, the pad electrode having a recess on a surface of the substrate, a protective film covering a part of the pad electrode other than the recess on the exposed surface, and a hydrogen absorbing film on the protective film and the recess of the pad electrode.

Abstract: An antenna apparatus utilizing an aperture of transmission line, which is connected to a first transmission line having a predetermined characteristic impedance, includes a tapered line portion, and an aperture portion. The tapered line portion is connected to one end of the transmission line, and the tapered line portion includes a second transmission line including a pair of line conductors. The tapered line portion keeps a predetermined characteristic impedance constant and expands at least one of a width of the transmission line and an interval in a tapered shape at a predetermined taper angle. The aperture portion has a radiation aperture connected to one end of the tapered line portion. A size of one side of the aperture end plane of the aperture portion is set to be equal to or higher than a quarter wavelength of the minimum operating frequency of the antenna apparatus.

Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: According to one embodiment, a method for wireless communication includes performing a first scan of a plurality of wireless channels of a wireless communication network by simultaneously utilizing at least two radios of a base station. The method also includes determining a channel quality metric for at least two of the wireless channels in response to the first scan. The method further includes selecting a first wireless channel of the plurality of wireless channels in response to determining the channel quality metrics. In addition, the method includes communicating on the first wireless channel utilizing the at least two radios of the base station.

Abstract: A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film.

Abstract: According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.

Abstract: A solid-state image pickup apparatus includes a pixel unit consisting of a plurality of pixels; a pixel control unit for controlling the plurality of pixels; a readout unit for reading a signal of each pixel output from the pixel unit; a shutter unit for establishing a state of a light incident to the pixel unit and that of shielding the pixel unit from the light; and a control unit. The control unit includes an exposure mode changeover unit for changing over an exposure mode to either a first exposure mode performing a simultaneous exposure for all pixels or a second exposure mode performing an exposure for each of a predetermined unit of pixels. The control unit controls the pixel control unit, readout unit and shutter unit according to an exposure mode changed over by the exposure mode changeover unit.

Abstract: A power supply device including a converter having a switch circuit to which an input voltage is supplied and a coil coupled between the switch circuit and an output end from which an output voltage is output; and a control circuit comparing between a feedback voltage and a reference voltage, and on/off controls the switch circuit according to a comparison result; wherein, the control circuit includes a current gradient detection circuit performs detection of a gradient of a coil current flows thorough the coil during an off period of the switch circuit and generates a slope voltage according to a result of the detection; and an adder circuit performs one of generating the feedback voltage by adding the slope voltage to a voltage according to the output voltage and generating the reference voltage by adding the slope voltage to a standard voltage that is set according to the output voltage.

Abstract: A semiconductor device fabrication method including: forming a gate conductor including a gate for a transistor in the first region, and a gate for a transistor in the second region, and a first film over a first stress film for covering the transistors; etching the first film from the second region by using a mask layer and etching the first film under the mask layer in the direction parallel to the surface of the semiconductor substrate by a first width from an edge of the first mask layer, and the first stress film from the second region; forming a second stress film covering the first stress film and the first film; etching the second stress film so that a portion of the second stress film overlaps a portion of the first stress film and a portion of the first film; and forming a contact hole connected with the gate conductor.

Abstract: An integrated circuit device includes a chip having a power supply terminal, a ground terminal, an input terminal, and an internal circuit formed therein. The chip comprises: a unidirectional device disposed between the input terminal and the ground terminal and directed from the ground terminal to the input terminal; and a ground open detection circuit including a first transistor having the gate connected to the input terminal and the source and the drain connected between the power supply terminal and the ground terminal, a second transistor having the gate connected to the ground terminal and the source and the drain connected between the power supply terminal and the ground terminal, and a comparator for comparing potentials of nodes respectively between drains of the first and second transistors and the power supply terminal, and for outputting a ground open detection signal.

Abstract: A semiconductor memory has a short transistor coupling complementary storage nodes of a latch circuit of a memory cell. A transfer transistor and the short transistor have a diffusion layer in common coupled to one of the storage nodes. The short transistor and a driver transistor have a diffusion layer in common coupled to the other storage node. The transfer transistor, the short transistor, and the driver transistor are continuously disposed via the diffusion layers in common, and thereby, variation of characteristics of the transfer transistor can be prevented. Accordingly, it may be possible to prevent that current supplying ability of the transfer transistor changes depending on a layout in the memory cell, and that an operation margin of the memory cell deteriorates.

Abstract: A relay board provided in a semiconductor device includes a first terminal, and a plurality of second terminals connecting to the first terminal by a wiring. The wiring connecting to the first terminal is split on the way so that the wiring connects to each of the second terminals.

Abstract: A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array, and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.