Abstract: A method of controlling a terminal device which receives display information from a host device and displays the display information on a screen includes the steps of displaying newest display information supplied from the host device in a predetermined area of the screen, and displaying previous display information in a remaining area of the screen, the previous display information having been supplied from the host device and once displayed as the newest display information in said predetermined area.

Abstract: A semiconductor memory device including a plurality of level converters, each of the level converters including a bridge circuit constituted by four MOS transistors having one type of conductivity, gates of one pair of four transistors opposing each other receiving a first signal and gates of the other pair of four transistors opposing each other receiving a signal complementary to the first signal; a pair of complementary MOS inverter circuits to which a second signal and a signal complementary to the second signal are input, respectively, the outputs of the pair of inverter circuits being connected to a first pair of connecting points positioned alternately in the bridge circuit, respectively; and a flip-flop circuit connected between a second pair of connecting points positioned alternately in the bridge circuit, to thereby output a third signal and a signal complementary to the third signal from the second pair of connecting points, resepctively.

Abstract: According to the present invention, an instruction address register unit I for reading instructions and an instruction address register unit II for indicating the address of the instruction being executed in the pipeline are provided independently. The address of a branching instruction is held in the instruction address register unit II until said instruction passes through the pipeline, the content of instruction address register unit I is updated when branching of the branching instruction is determined, and thereby delay in reading an instruction after 8 bytes at the branching address can be reduced.

Abstract: A modulation device using multi-level digital signals includes: a pair of balanced mixers for carrying out quadrature amplitude modulation to deliver a quadrature amplitude modulated signal; input and output hybrid circuits, connected to carrier input terminals of the pair of balanced mixers, for supplying carrier inputs to the pair of balanced mixers; and a modulation characteristic compensation unit connected with input terminals of the pair of balanced mixers for supplying the pair of balanced mixers with orthogonal baseband input signals.