Patents Assigned to Full Circle Research, Inc.
  • Patent number: 6878595
    Abstract: The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing latchup sensitivity by a step to be performed after the IC has been manufactured, rather than being a step in the normal production process. The process involves exposing silicon, either in wafer or die form, to energetic ions, such as protons (hydrogen nuclei) or heavier nuclei (e.g. argon, copper, gold, etc.), having energy sufficient to penetrate the silicon from the back of the wafer or die to within a well-defined distance from the surface of the silicon on which the integrated circuit has been formed (the front surface).
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: April 12, 2005
    Assignee: Full Circle Research, Inc.
    Inventor: James P Spratt
  • Publication number: 20040147080
    Abstract: The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing latchup sensitivity by a step to be performed after the IC has been manufactured, rather than being a step in the normal production process. The process involves exposing silicon, either in wafer or die form, to energetic ions, such as protons (hydrogen nuclei) or heavier nuclei (e.g. argon, copper, gold, etc.), having energy sufficient to penetrate the silicon from the back of the wafer or die to within a well-defined distance from the surface of the silicon on which the integrated circuit has been formed (the front surface).
    Type: Application
    Filed: January 27, 2003
    Publication date: July 29, 2004
    Applicant: Full Circle Research, Inc.
    Inventor: James P. Spratt
  • Patent number: 6476597
    Abstract: A method for testing IC devices for radiation hardness in a non-destructive manner, comprising subjecting a device under test (DUT) originally in an insensitized state, to a state in which the DUT is more sensitive to adverse effects of ionizing dose radiation and while the DUT is in the more sensitive state, subjecting the DUT to a low level of ionizing radiation to degrade performance of the DUT and electrical testing followed by a restoration of the DUT to its original insensitized state.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: November 5, 2002
    Assignee: Full Circle Research, Inc.
    Inventors: James P Spratt, Roland E. Leadon