Abstract: A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.

Abstract: This disclosure describes techniques for performing communications between devices using various aspects of Ethernet standards. As further described herein, a protocol is disclosed that may be used for communications between devices, where the communications take place over a physical connection complying with Ethernet standards. Such a protocol may enable reliable and in-order delivery of frames between devices, while following Ethernet physical layer rules, Ethernet symbol encoding, Ethernet lane alignment, and/or Ethernet frame formats.

Abstract: A system comprises a data processing unit (DPU) integrated circuit having programmable processor cores and hardware-based accelerators configured for processing streams of data units; and software executing on one or more of the processing cores. In response to a request to perform an operation on a set of one or more data tables, each having one or more columns of data arranged in a plurality of rows, the software configures the DPU to: input at least a portion of the rows of each of the database tables as at least one or more streams of data units, process the one or more streams of data units with the hardware-based accelerators to apply one or more of compression, encoding or encryption to produce a resultant stream of data units; and write the resultant stream of data units to a storage in a tree data structure.

Abstract: A key-value store supporting GET, PUT and DELETE operations, serializes multiple clients using two locks, and that supports asynchronous resizing. The locking scheme includes an operation of holding two locks, one for the key involved in the operation, one for the page currently searched or updated. The store can either be a single volume holding keys and data or can be organized as a directory volume referencing a number of data volumes organized by data-size ranges. The scheme also supports asynchronous resizing of the directory while continuing to perform operations.

Abstract: This disclosure describes techniques that include associating a timestamp with a network packet, and carrying the timestamp or otherwise associating the timestamp with the network packet during some or all processing by the system described herein. In one example, this disclosure describes a method that includes receiving, at an ingress port of a device, an initial portion of a network packet; storing, by the device, timestamp information associated with receiving the initial portion of the packet; and determining, by the device, whether to transmit information derived from the initial portion of the network packet.

Abstract: In one example, a data processing unit (DPU) includes a host unit interface for communicatively coupling to second device via a serial input/output (I/O) connection, and a control unit implemented in circuitry and configured to initially configure the host unit interface of a data processing unit to operate in endpoint mode, determine that the host unit interface of the data processing unit is to switch from operating in the endpoint mode to root complex mode, in response to determining that the host unit interface is to switch from operating in the endpoint mode to the root complex mode: configure the host unit interface to operate in the root complex mode, and send data to an I/O expander unit to cause the I/O expander unit to issue a reset signal to the second device, the second device being configured to operate in the endpoint mode.

Abstract: This disclosure describes techniques for addressing and/or accounting for path failures (e.g., congestion, link failures, disconnections, or other types of failures) within a network environment. In one example, this disclosure describes a method that includes receiving, by a node connected to a plurality of interconnected nodes, a network packet to be forwarded to a destination node; identifying, by a forwarding plane within the node, a first link along a path to the destination node; determining, by the forwarding plane, that the first link is inoperable; storing, by the node and within the network packet, data identifying the node as having been visited; identifying, by the forwarding plane and from among the plurality of egress links from the node, a second link that is operable and is along an alternative path to the destination node; and transmitting the network packet over the second link.

Abstract: This disclosure describes techniques that include representing, traversing, and processing directed graphs using one or more content-addressable memory devices. In one example, this disclosure describes a method that includes presenting query data to one or more ternary content-addressable memory (TCAM) devices, wherein the query data includes state data and key data; receiving, from the TCAM devices, information about a matching address identified by the TCAM devices; accessing, based on the information about the matching address, information in one or more storage devices; performing, based on the information in the one or more storage devices, at least one operation on data included within the one or more storage devices to generate processed data; outputting the processed data; determining, based on the information in the one or more storage devices, new state data and a new key value; and presenting new query data to the TCAM devices.

Abstract: A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. This disclosure describes examples of retrieving values represented by one or more previous symbols needed for decoding a current symbol before or in parallel with the insertion of the values represented by the one or more previous symbols in the data stream.

Abstract: A fabric control protocol is described for use within a data center in which a switch fabric provides full mesh interconnectivity such that any of the servers may communicate packet data for a given packet flow to any other of the servers using any of a number of parallel data paths within the data center switch fabric. The fabric control protocol enables spraying of individual packets for a given packet flow across some or all of the multiple parallel data paths in the data center switch fabric and, optionally, reordering of the packets for delivery to the destination. The fabric control protocol may provide end-to-end bandwidth scaling and flow fairness within a single tunnel based on endpoint-controlled requests and grants for flows. In some examples, the fabric control protocol packet structure is carried over an underlying protocol, such as the User Datagram Protocol (UDP).

Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.

Abstract: Timer management techniques are described. An example processing device includes a memory configured to store successive wheels available to be included in traversal paths for timers running on the device, each wheel representing a queue of timers, each wheel having a different, corresponding time delay (TO) value for queuing a timer, and processing circuitry in communication with the memory. The processing circuitry is configured to determine, in response to a request for a timer, a total traversal time for the timer, to select, from the stored wheels, a subset of wheels such that a sum of the respective TO values of the selected subset is within a predetermined margin of error with respect to the total traversal time for the timer, and to sequence the selected subset of wheels based on the respective TO values of the selected subset of wheels to form a traversal path for the timer.

Abstract: Aspects of this disclosure describes techniques for parsing network packets, processing network packets, and modifying network packets before forwarding the modified network packets over a network. The present disclosure describes a system that, in some examples, parses network packets, generates data describing or specifying attributes of the network packet, identifies operations to be performed when processing a network packet, performs the identified operations, generates data describing or specifying how to modify and/or forward the network packet, modifies the network packet, and outputs the modified packet to another device or system, such as a switch.

Abstract: This disclosure describes techniques for providing early acknowledgments to a source device performing a data write operation within a data center or across a geographically-distributed data center. In one example, this disclosure describes a method that includes receiving, by a gateway device and from a source device within a local data center, data to be stored at a remote destination device that is located within a remote data center; storing, by the gateway device, the data to high-speed memory included within the gateway device; transmitting, by the gateway device, the data over a connection to the remote data center; after transmitting the data and before the data is stored at the remote destination device, outputting, by the gateway device to the source device, a local acknowledgment, wherein the local acknowledgment indicates to the source device that the data can be assumed to have been stored at the remote destination device.

Abstract: An example integrated circuit includes a memory including a non-deterministic finite automata (NFA) buffer configured to store a plurality of instructions defining an ordered sequence of instructions of at least a portion of an NFA graph, the portion of the NFA graph comprising a plurality of nodes arranged along a plurality of paths. The NFA engine determines a current symbol and one or more subsequent symbols of a payload segment that satisfy a match condition specified by a subset of instructions of the plurality of instructions for a path of the plurality of paths and in response to determining the current symbol and the one or more subsequent symbols of the payload segment that satisfy the match condition, outputs an indication that the payload data has resulted in a match.

Abstract: A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. This disclosure describes a hardware-based programmable data compression accelerator for the data processing unit including a pipeline for performing string substitution. The disclosed string substitution pipeline, referred to herein as a “search block,” is configured to perform string search and replacement functions to compress an input data stream. In some examples, the search block is a part of a compression process performed by the data compression accelerator. The search block may support single and multi-thread processing, and multiple levels of compression effort.

Abstract: This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.

Abstract: An example processing device includes a memory including a discreet finite automata (DFA) buffer configured to store at least a portion of a DFA graph, the DFA graph comprising a plurality of nodes, each of the nodes having zero or more arcs each including a respective label and pointing to a respective subsequent node of the plurality of nodes, at least one of the plurality of nodes comprising a match node, wherein the at least portion of the DFA graph comprises one or more slots of a memory slice, the one or more slots comprising data representing one or more of the arcs for at least one node of the plurality of nodes, and a DFA engine implemented in circuitry, the DFA engine comprising one or more DFA threads implemented in circuitry and configured to evaluate a payload relative to the DFA graph.

Abstract: A network system for a data center is described in which a switch fabric may provide full mesh interconnectivity such that any servers may communicate packet data to any other of the servers using any of a number of parallel data paths. Moreover, according to the techniques described herein, edge-positioned access nodes, optical permutation devices and core switches of the switch fabric may be configured and arranged in a way such that the parallel data paths provide single L2/L3 hop, full mesh interconnections between any pairwise combination of the access nodes, even in massive data centers having tens of thousands of servers. The plurality of optical permutation devices permute communications across the optical ports based on wavelength so as to provide, in some cases, full-mesh optical connectivity between edge-facing ports and core-facing ports.

Abstract: A switch box approach to routing interconnects during the design of an integrated circuit (IC). Processing circuitry (e.g., via an automation tool) may determine a manner in which to interconnect functional blocks of the IC. The signal routes that interconnect the functional blocks can become complicated to comply with design rules for latency, crosstalk, etc. The processing circuitry may divide channels between functional blocks into multiple interconnection blocks, called channel blocks. In this way, the channel blocks may be considered as another block type (e.g., interconnection block) that the processing circuitry can leverage for routing signals between functional blocks.