Abstract: A multi-mode wireless device on a single substrate includes an analog portion and a digital portion integrated on the single substrate. The analog portion includes a cellular radio core; and a short-range wireless transceiver core. The digital portion integrated on the substrate includes a reconfigurable processor core coupled to the cellular radio core and the short-range wireless transceiver core, the reconfigurable processor adapted to handle a plurality of wireless communication protocols. The digital portion also includes a high-density memory array core coupled to the reconfigurable multi-processor core.

Abstract: An apparatus captures a digital image from a film-based camera having a chamber to receive a film cartridge and a take-up spool to advance the film after each shot. The apparatus includes a cartridge shaped to fit in the camera film chamber, the cartridge including a processor, a storage unit coupled to the processor, and an input output unit coupled to the processor. The cartridge houses a flexible strip having one end coupled to the cartridge and the other end adapted to be wound on the camera take-up spool, the flexible strip containing one or more imaging arrays deposited thereon to capture the digital image, each of the imaging arrays communicating with the processor.

Abstract: Systems and methods are disclosed for parallel testing one or more wireless devices using a single wireless command, each device including a processor and memory coupled to the processor. The system includes a tester adapted to exercise the wireless devices, including: a transceiver adapted to communicate with each wireless device; and a computer coupled to the transceiver, the computer adapted to test all wireless devices in parallel by issuing a single test command using a wireless signal, the computer adapted to store test patterns and test results.

Abstract: A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of each processing unit to optimize speed and processing power for a task; and a high-density memory array core coupled to the processing units.

Abstract: Apparatus and method for securing a wireless communication medium are disclosed. The apparatus uses a Subscriber Identity Module (SIM) card. The method includes determining a SIM card insertion and if so, accessing SIM data and transmitting the SIM data to a base station for comparison with a local copy of authorized user data file; granting mobile unit access to base station if the information matches and otherwise indicating an access failure.

Abstract: Systems and methods are disclosed for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and a duty cycle. The system changes the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the clock; and generates a low-interference clock having the changed duty cycle while keeping the predetermined frequency.

Abstract: A self-calibrating integrated circuit includes a processor having at least one analog function used with the processor; one or more sensors adapted to sense one or more environmental parameters of the at least one analog function; and a solid state memory being configured to store the one or more environmental parameters of the at least one analog function.

Abstract: A digital camera that operates inside and in conjunction with a non-digital camera, enabling the user to continue to use the non-digital camera, controls and associated lens, flashes, etc. The digital camera includes an imager which senses the image to be recorded and a light detector which detects the existence of light due to the opening of the shutter aperture of the non-digital camera. The light detector controls the imager such that an image is recorded and output from the imager when the light detector detects the opening of the shutter aperture which occurs when the photographer depresses the shutter button to take a picture. Preferably the digital camera includes a memory for storage of the images recorded. These images can then be subsequently output to an external device for further processing or display.

Abstract: Systems and methods wirelessly communicate data over a plurality of cellular channels by requesting an allocation of cellular frequency channels from a mobile station to a base station; allocating available frequency channels in response to the request from the mobile station; and bonding the available frequency channels to communicate data.

Abstract: A high capacity silicon capacitor formed on an integrated circuit substrate includes a metal portion on the substrate; a silicon nitride (SiN) portion sputtered on the metal; a silicon (Si) portion sputtered on the silicon nitride portion, another SiN layer and finally a metal layer. The SiN layers are for increased isolation and are optional.

Abstract: A method to determine position of a user includes sniffing for one or more earth-based media; and if the one or more earth-based media exists, using an earth-based positioning system (PS) receiver associated with one of the media and otherwise using a satellite-based PS receiver.

Abstract: A low power a reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.

Abstract: A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of each processing unit to optimize speed and processing power for a task; and a high-density memory array core coupled to the processing units.

Abstract: A transformation engine includes an address generator; a butterfly unit coupled to the address generator; a twiddle LUT coupled to the address generator; and a multiplier having a first input coupled to the butterfly unit and a second input coupled to the twiddle LUT.

Abstract: An apparatus captures a digital image from a film-based camera having a chamber to receive a film cartridge and a take-up spool to advance the film after each shot. The apparatus includes a cartridge shaped to fit in the camera film chamber, the cartridge including a processor, a storage unit coupled to the processor, and an input output unit coupled to the processor. The cartridge houses a flexible strip having one end coupled to the cartridge and the other end adapted to be wound on the camera take-up spool, the flexible strip containing one or more imaging arrays deposited thereon to capture the digital image, each of the imaging arrays communicating with the processor.

Abstract: A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; a wireless transceiver transmitting and receiving at a frequency based on a wireless clock input; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units and the wireless clock input, the clock outputs being generated from a common master clock.

Abstract: An apparatus compensates for voltage and temperature variations on an integrated circuit with: a voltage sensor having a digital voltage output; a temperature sensor having a digital temperature output; a register coupled to the voltage sensor and the temperature sensor, the register adapted to concatenate the digital voltage output and the temperature output into an address output; and a memory device having an address input coupled to the address output of the register, the memory device being adapted to store one or more corrective vectors.

Abstract: A self-calibrating integrated circuit includes a processor having at least one analog function used with the processor; one or more sensors adapted to sense one or more environmental parameters of the at least one analog function; and a solid state memory being configured to store the one or more environmental parameters of the at least one analog function.