Abstract: Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor. The source/drains of the sense field effect transistor are formed from buried doped layers (e.g. N+ in a P-doped substrate) which are formed prior to formation of the polysilicon floating gate and control gate. Lateral diffusion of dopant from the buried source/drains into the channel beneath the floating gate facilitates electron tunneling during erase and program operations, and the graded junctions of the buried source/drains lower band-to-band tunneling leakage.
Type:
Grant
Filed:
December 4, 1998
Date of Patent:
October 24, 2000
Assignee:
GateField Corporation
Inventors:
Jack Zezhong Peng, Volker Hecht, Robert M. Salter, III, Kyung Joon Han, Robert U. Broze
Abstract: In an FPGA, nonvolatile reprogrammable interconnect cells which have a switch transistor and at least one second transistor for programming and sensing, or a second transistor for sensing and a buried N+ region for programming the cell, use a high voltage on the common control gate for the cell erasing operation. The source/drains of the switch transistor are grounded. By placing an intermediate voltage on the source/drains of the second transistor, erase times can be reduced and test costs can be significantly lowered.
Abstract: Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected through a buried bitline in juxtaposition with the switch transistor and the sense transistor over which are the floating gate and the control gate. The sense transistor can be fabricated simultaneously with fabrication of the switch transistor whereby the two transistors are identical in dopant concentrations.
Type:
Grant
Filed:
December 4, 1998
Date of Patent:
June 6, 2000
Assignee:
GateField Corporation
Inventors:
Jack Zezhong Peng, Robert M. Salter, III, Volker Hecht, Kyung Joon Han, Robert U. Broze, Victor Levchenko
Abstract: The present invention provides for an improved EPROM transistor cell which forms the programming portion of the programmable interconnect interconnect of an FPGA integrated circuit, and a method of manufacturing the EPROM cell. The EPROM cell has a floating gate disposed over a P region of the substrate. Aligned with one edge of the floating gate and at the surface of the substrate is a lightly doped P- region; on the opposite edge of the floating gate is a heavily doped N+ region. A control gate lies over the P-, P substrate and over the N+ region. N+ regions are formed at the opposite edges of the control gate. One N+ region is contiguous to the P- region and forms the source of the EPROM cell and the other N+ region is connected to the N+ region under the control gate and forms the drain of the EPROM cell. This structure allows for easy process control of the V.sub.
Type:
Grant
Filed:
August 9, 1996
Date of Patent:
April 13, 1999
Assignee:
GateField Corporation
Inventors:
Jack Zezhong Peng, Robert U. Broze, Kyung Joon Han, Victor Levchenko
Abstract: Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor.
Type:
Grant
Filed:
March 31, 1997
Date of Patent:
November 17, 1998
Assignee:
GateField Corporation
Inventors:
Robert M. Salter, III, Kyung Joon Han, Jack Zezhong Peng, Victor Levchenko, Robert V. Broze
Abstract: A programmable interconnect which closely integrates an independent switching transistor with separate NVM programming and erasing elements. The programming element is an EPROM transistor and the erasing element is a Fowler-Nordheim tunneling device. A unitary floating gate is shared by the switching transistor and the NVM programming and elements which charge and discharge the floating gate. The shared floating gate structure is the memory structure of the integrated programmable interconnect and controls the impedance of the switching transistor.
Type:
Grant
Filed:
November 21, 1996
Date of Patent:
June 9, 1998
Assignee:
Gatefield Corporation
Inventors:
Robert J. Lipp, Richard D. Freeman, Robert U. Broze, John M. Caywood, Joseph G. Nolan, III