Abstract: In a digital processing system in which a plurality of control units communicate with each other and with memory over a common bus, an arbitration circuit associated with each of the control units tests for priority among the units requesting access to the bus, granting access to the highest priority unit as soon as the bus is not busy. Priority is determined by priority numbers assigned to each unit. Priority is tested simultaneously in each unit in synchronism, each unit using common lines on the bus for both input and output to establish which unit has highest priority.

Abstract: A priority arbitration circuit for resolving priority between a plurality of master devices which compete for access to one or more slave devices over a common bus. All master devices share a common Request line and a common Busy line. Priority is passed along serially from one device to another in sequence until all pending requests have been serviced, after which priority reverts to an initial device. The first device to issue a request gains priority. Simultaneous requests are resolved in the order in which the devices are connected in the priority chain. A device having a local request and receiving priority on the priority chain sets the Busy signal to lock out all other devices.

Abstract: An apparatus and method are disclosed for substantially improving the accuracy and surface finish quality of numerical control machine tool performance by generating velocity command signals for multiple axis drive systems based on the distance between the cutting tool and a point along the desired path, either the desired end point or a dynamic target which moves continuously along the desired cutting path ahead of the cutting tool.