Abstract: An automatic detection and selection circuit resident in a DCE is provided. The circuit is coupled to the DCE interface connector and detects receipt by the DCE of V.35 and RS-232 transmit data signals, distinguishes between those signals, and selects circuitry for passing the data therethrough. The circuit comprises a switch coupled to a first TX data terminal (pin 2 or P) of the DCE interface connector, first and second line receiving circuits, a microprocessor, and a relay. The first line receiving circuit is coupled to a first pole of the switch and to the second TX data terminal (pin S) of the DCE interface connector and provides indications as to whether or not an input signal is present at at least one of pins P and S. The second line receiving circuit is coupled to the second pole of the switch and provides indications as to whether or not a valid RS-232 transmit data signal is detected.

Abstract: A method for identifying a V.fast modem within already standard automatic interworking procedures are provided. The method comprises utilizing standard methods for identifying a V.32/V.32bis modem up and through the standard ranging sequence, and after ranging and during the undefined 8192 baud period before an S signal would be sent by a V.32 or V.32bis modem the answering mode modem sends a predetermined signal (VFS) which does not resemble an S signal. Simultaneous with the answer modem sending VFS, the call mode modem looks for VFS. Upon detecting VFS, the call mode modem confirms receipt by sending a confirming signal (VFC) to the answer mode modem. Upon receiving VFC, if the communicating modems are not already in a problem mode, the modems will probe the line and continue according to whatever V.fast standards will be adopted. Preferably, VFS contains at least two tones. If desired, VFS can be a spectrum, with energy in frequency bands surrounding the S tone frequencies suppressed.

Abstract: A transmitter is provided with a distribution preserving Tomlinson coder which predistorts shaped data signals such that the power of each data signal exiting the coder is substantially similar to the power of the data signal entering the coder and such that upon transmission of the predistorted data signal over a channel, the effect of ISI of the channel is substantially removed. The transmitter is primarily intended for coded modulation systems utilizing a "coset" code, and the predistortion is preferably accomplished according to a linear function ##EQU1## where r.sub.k is a data signal entering the coder, a and.sub.i b.sub.i are the coefficients of polynomials relating to the channel impulse response, x.sub.k is the predistorted data signal exiting the coder, and s.sub.k is chosen to cause the signal power of x.sub.k on average to approximately equal the signal power of r.sub.k on average. Different methods for so choosing s.sub.k are disclosed.

Abstract: Methods for improving modem performance and apparatus incorporating the methods are provided. The preferred methods comprise measuring the signal/noise ratio and intermodulation distortion (IMD) relating to signals being transmitted over a channel, and adjusting the transmitting power of the transmitting modem below a maximum permissable power in response to the measurements in order to reduce the error rate of the data transmission, the error rate being a function of both the signal/noise ratio and the IMD. Theoretically, the power can be adjusted to an optimal level, as the decrease in power increases the error rate due to signal/noise ratio according to a first function, but decreases the error rate due to IMD according to a second function. A first preferred manner of determining the final power level to be utilized is to calibrate a modem according to the techniques (e.g., Trellis precoding, etc.

Abstract: A transmitter is provided with a distribution preserving Tomlinson coder which predistorts shaped data signals such that the power of each data signal exiting the coder is substantially similar to the power of the data signal entering the coder and such that upon transmission of the predistorted data signal over a channel, the effect of ISI of the channel is substantially removed. The transmitter is primarily intended for coded modulation systems utilizing a "coset" code, and the predistortion is preferably accomplished according to a linear function ##EQU1## where r.sub.k is a data signal entering the coder, a.sub.l and b.sub.l are the coefficients of polynomials relating to the channel impulse response, x.sub.k is the predistorted data signal exiting the coder, and s.sub.k is a multiple of a given value (N) which is chosen to cause x.sub.k and r.sub.k to occupy identical defined regions in space, where the total length of each defined region is the given value N.

Abstract: A pluggable electrical connector is provided having contact elements with first ends soldered to a daughter board, mid-sections which are crimped and bent through ninety degrees, and second ends which have a converging portion and which terminate in bifurcated conical contact portions which make contact with the rims of contact-quality plated through holes of a mother board. By causing contact between the rim and the cone surface, normal forces greater than the mating force are generated. The connector housing includes self-centering funnel openings adjacent the mother board for centering the converging portions of the contact elements therein in a nominal position and for acting as a preloading stop. The housing also includes side-wall locking tabs which hold adjacent rows of contacts at identical fixing points relative to the ninety-degree bend to ensure identical spring parameters for all contact elements.

Abstract: Electrical connectors are provided with spring contact elements each having a tapered contact portion for mating with the plated rim of a hole. The tapered contact portion can be configured as a bifurcated cone, a suitably shaped wire, or other tapered, flexible contact. Besides the contact portion, the contact elements also include spring portions which can assume various configurations and tail portions which can also assume various configurations. Where the tapered contact portion is a suitably shaped wire, the spring portion and the contact portion are essentially the same. The tail portions can be arranged to have tapered contact portions where permanent connection of the tail is not desired. The disclosed electrical connectors have housings for the spring contact elements, and a first make, last break function can be provided by configuring the housings appropriately. The holes with which the tapered spring contact elements mate can be part of a printed circuit board, a flex circuit, or other object.

Abstract: An integrated circuit package is provided with a plurality of contact element leads, each lead having a first portion for making electrical connection with the integrated circuit and a second tapered contact portion for mating with a conductive rim of the hole of a circuit board. In conjunction with the integrated circuit package, a fastener is provided for holding the tapered contact elements in mating relationship with the conductive rims. The tapered contact portion of the lead of the integrated circuit package may take any of various forms, as long as the lead is tapered and resilient so that proper mating with a conductive rim can be accomplished. Likewise, the fastener which holds the tapered contact elements in mating relationship with the conductive rims may take any of numerous forms. All that is required is that the fastener couple to both the circuit board and the integrated circuit package, and that the integrated circuit package be removable from the fastener.

Abstract: Apparatus and methods for automatically determining the bit rate of an incoming signal are provided. The apparatus includes a counter, a logic circuit, and a histogram generating circuit. The counter counts the number of fast reference clock cycles which fit within each pulse of the incoming signal for a statistically significant number of pulses and provides indications thereof to the logic circuit. The logic circuit associates each of the indications with one of a plurality of allowable bit rates. The histogram generating circuit tracks the numbers of times the counts are associated with each allowable bit rate. In one embodiment, the allowable bit rate most often chosen is determined to be the bit rate of the incoming signal. In another embodiment, if a DDS1 line rate is determined to be the bit rate most often chosen, the DDS2 rate associated with the DDS1 line rate is provisionally selected.

Abstract: Methods for embedding additional information (e.g. a password function) in a handshake of communicating modems is provided. An auxiliary packet containing the additional information is placed in the handshake sequence of an originating modem in such a manner that it cannot be confused by the receiving modem with other signals which are required to be sent by the originating modem in the modem handshake. The answering modem looks for the auxiliary packet, and if the auxiliary packet is not received, or if the information in the auxiliary packet is not sufficient to establish authorization, the answering modem causes the call to be dropped. In V.32 type modems, the auxiliary packet is placed by the originating modem somewhere in the training sequence (TRN) after the required twelve hundred eighty symbol intervals, and before the R2 sequence, and the auxiliary packet is generated in such a manner that it cannot be confused with the R2 sequence.

Abstract: A mapping technique for an 8D, sixty-four state convolutionally coded 19.2 Kbit/second modem utilizes twenty-nine bits for defining all points of an 8D constellation. The 8D constellation which is mapped is comprised of a desired subset of a concatenation of four 2D constellations, where each 2D constellation has one hundred ninety-two points. The mapping technique generally comprises: dividing each 2D constellation into six different energy groups of thirty-two points each, the concatenation of four groups, one from each 2D constellation, comprising an 8D grouping; choosing five hundred twelve 8D groupings from the possible one thousand two hundred ninety-six (6.sup.

Abstract: A mapping technique for an 8D, sixty-four state convolutionally coded 19.2 Kbit/second modem utilizes twenty-nine bits for defining all points of an 8D constellation. The 8D constellation which is mapped is comprised of a desired subset of a concatenation of four 2D constellations, where each 2D constellation has one hundred sixty points. The mapping technique generally comprises: dividing each 2D constellation into five different energy groups of thirty-two points each, the concatenation of four groups, one from each 2D constellation, comprising an 8D grouping; choosing five hundred twelve 8D groupings from the possible six hundred twenty-five (5.sup.

Abstract: A pluggable electrical connector is provided having contact elements with first ends soldered to a daughter board, midsections which are crimped and bent through ninety degrees, and second ends which have a converging portion and which terminate in bifurcated conical contact portions which make contact with the rims of contact-quality plated through holes of a mother board. By causing contact between the rim and the cone surface, normal forces greater than the mating force are generated. The connector housing includes self-centering funnel openings adjacent the mother board for centering the converging portions of the contact elements therein in a nominal position and for acting as a preloading stop. The housing also includes side-wall locking tabs which hold adjacent rows of contacts at identical fixing points relative to the ninety-degree bend to ensure identical spring parameters for all contact elements.

Abstract: A system under the hand held control of a user for providing three dimensions of input to a computer processor while operating on an essentially planar surface is disclosed.

Abstract: A digital signal processor (DSP) for conducting arithmetically complex functions, is provided. The DSP is preferably embodied as a single integrated circuit chip and generally includes a microinstruction sequencer (MIS) section, an arithmetic logic unit (ALU), a serial arithmetic processor section, a RAM section, and a system data bus. The MIS includes a coded ROM, a circuit for addressing the ROM, a ROM decoder for decoding the ROM code into control and data signals, and circuitry for sending the control and data signals to desired locations, and controls the functioning of the DSP. The ALU performs arithmetic and logic functions under the control of the ROM, while the serial arithmetic processor section conducts arithmetically complex functions under the control of the ROM. The RAM, under control of the ROM receives and stores data which is sent to the RAM via a system data bus directly from the ROM, from the ALU, from the serial arithmetic processor, and from circuitry exterior to the DSP.

Abstract: An intelligent synchronous modem and data communication systems utilizing the intelligent synchronous modem are provided. The modem comprises: at least one connector having a first and a second port for primary and secondary channels of communication with a host computer, wherein the primary communication channel is for communication of synchronous data and the secondary communication channel is for communication of asynchronous data; a microprocessor for recognizing and executing commands of the host computer, wherein the commands are in the form of asynchronous data received over the secondary communication channnel; and interface means for interfacing the microprocessor with telephone lines, wherein synchronous data received by the microprocessor is sent to the interface means.

Abstract: An encoder is provided for generating rotationally invariant trellis codes when used with a signal constellation having m subconstellations indexed by j, each subconstellation having a plurality of points, where each subconstellation is a distinct rotation by j(360/m) degrees of another subconstellation such that no subconstellation has a point in common with another subconstellation. The encoder has a state block and a state update block. The state means receives q inputs i, and generates m outputs j, where m=pq and where p and q are integers greater than one and have no common factors. Outputs m are generated according to inputs i and states s of the state block according to j=i mod q and jd=s mod p, where the state block can assume n states, and n=md where d is an integer greater than one and has no common factors with p.

Abstract: A microinstruction sequencer capable of directing an arithmetic-logic unit to conduct conditional operations is disclosed and generally includes a ROM and a selection circuit. The ROM has a memory of m bits wide and n words long, wherein for an m bit wide word in the ROM which defines a conditional operation, a first plurality of bits of the m bits are allocated to a first set of bits for instructing the arithmetic-logic unit as to the function it is to perform, a second plurality of bits of the m bits are allocated to a second set of bits for instructing the arithmetic-logic unit as to the function it is to perform, and a third plurality of bits of the m bits are allocated to a set of control bits. The selecting circuit selects one set of bits from at least the first and second set of bits, and includes a controller for receiving the control bits and controlling the selection by the selection circuit in response thereto.

Abstract: An algorithm for ordering selects for a plurality of channels to be multiplexed into a frame is provided. A channel ready counter and a channel select position counter for each of the channels to be multiplexed are initialized. The first and succeeding channel selects are chosen based primarily on the respective values of the channel ready counters such that a channel having a ready counter of relative higher value is always selected before a channel having a ready counter of relative lower value. Where channel ready counter integer values of more than one channel are equal, the select is chosen on the secondary basis of channel rate, with the highest rate channel of the highest ready count contributing first. After a select is made, the ready counter of the selected channel is determined, and the position counters of the channels are decremented by a value corresponding to the number of selects for that channel in the frame.

Abstract: A parallel arithmetic-logic unit (PALU) controlled by a microinstruction sequencer and capable of executing conditional operations in a single pass is disclosed. The PALU generally comprises first and second registers for storing data, a comparator for continually comparing the values in the registers, and an arithmetic-logic core connected to the registers for performing arithmetic, logical and data move operations on the data in the registers. The comparator is preferably an unsigned magnitude comparator which outputs flags indicative of the relative status of the values in the registers. The flags are read by a microinstruction sequencer which then uses the flag information to determine what operation the arithmetic-logic core is to conduct. Preferably, a shifter is also provided between one of the registers and the arithmetic-logic core.