Abstract: A method for retrieving and managing addresses is provided. The steps may include of receiving, at a first buffer of m buffers, a request for an address; obtaining the address from a corresponding first register of the m registers; sending the address, received by said obtaining, to a destination; storing the address, received by the obtaining, in the first buffer; and clearing the contents of a second buffer of the m buffers, in response to any of said receiving, obtaining or storing, without clearing the contents of said first buffer, wherein m is a positive integer.

Abstract: The present invention comprises cost-effectively manufactured, electrically conductive and mechanically compliant micro-leads and a method of utilizing these compliant micro-leads to interconnect area grid array chip scale packages (“CSPs”) to printed wiring boards (“PWBs”). The preferred method includes orienting a plurality of conductive compliant micro-leads, secured to one another in parallel with tie bars and tooling, to align with a corresponding pattern of conductive pads located along the surface of an area grid array CSP. The compliant micro-leads are electrically connected and mechanically secured to the corresponding connecting surfaces of the area grid array CSP. Next, the securing tie bars and the tooling are removed. The opposite ends of the conductive compliant micro-leads are then oriented to align with a corresponding pattern of conductive surface pads on a PWB.

Abstract: An apparatus and method for adjusting the clock delay in systems with multiple integrated circuits has a controller, a programmable clock generator and a plurality of integrated circuits, each integrated circuit including a data flip-flop, a programmable delay and a clock-fanout tree, wherein the clock delay in the integrated circuits is adjusted to match the inherent delay in the integrated circuit having the longest inherent delay.

Abstract: A system and method for beamforming signals received in sparse, irregular sensor arrays has a network of sensors organized into sensor clusters, a signal processing node for each sensor cluster for beamforming the signals received by the sensors in each sensor cluster and an aggregation node for combining the beamformed responses from each sensor cluster to form a composite response characterized by minimized side lobes and grating lobes.

Abstract: An electrical connector assembly using conventional signal pins is adapted for use with impedance-controlled cables by dividing the body of the connector into one or more separate channels. Each channel is defined by a perimeter providing electrical shielding. A separate impedance-controlled wire or cable can be terminated at conventional signal pins installed in an insert located within a particular channel. A transition region between a connector plug or receptacle and an incoming wire or cable preserves the correct impedance characteristics of the cable.

Abstract: A method and system of utilizing inexpensively manufactured, electrically conductive and mechanically compliant disks to interconnect an area grid array (“AGA”) chip to a printed wiring board. The conductive disk shaped leads are stamped from a thin sheet of conductive material. To increase solderability and protect the disk surface, the disks can be plated with tin or an equivalent material. Each disk is positioned tangent to the surface of an AGA chip in a specific orientation. One edge of each disk is electrically connected and mechanically secured to a corresponding conductive pad located on the surface of the AGA chip. The opposite edge of each conductive disk is positioned to align with a corresponding conductive surface pad on a printed wiring board (“PWB”). Each opposite edge is electrically connected and mechanically secured to the surface of the PWB, thereby establishing a compliant electrical connection between the AGA chip and the PWB.

Abstract: A method for assembling an impedance controlled connector using conventional connector shells and inserts and corresponding connector pins and sockets. Controlled impedance cables are prepared and physically arranged for termination in a conventional connector shell in a configuration which enhances the impedance control characteristic of the assembled connector. Assembly of the connector is effected using conventional materials and tools.

Abstract: A device for storage of electronic data has a sealed hard drive component that can be mounted directly to a circuit board. The device can house a plurality of individual hard drives in a stacked configuration. The stacked hard drives are encased within a hermetically sealed housing, the exterior of which has connectors suitable for mounting directly to a circuit board. At least two of the hard drives encased within the housing can be controlled by a single hard drive controller located inside or outside the housing.

Abstract: A computer system uses redundant voting at the hardware clock level to detect and to correct single event upsets (SEU) and other random failures. In one preferred embodiment, the computer includes four or more commercial processing units (CPUs) operating in strict "lock-step" and whose outputs (33, 37) to system memory and system bus are voted by a gate array which may be implemented in a custom integrated circuit. A custom memory controller interfaces to the system memory and system bus. The data and address (35, 37) at each write to and read from memory within the computer are voted at each CPU clock cycle. A vote status and control circuit "reads" the status of the vote and controls the state of the CPUs using hardware and software. The majority voted signals are used by the agreeing CPUs 32 to continue processing operations without interruption.

Abstract: A method and apparatus is provided for connecting area grid array semiconductor chips to a printed wire board. A compliant lead matrix includes a carrier and a plurality of conductive leads arranged parallel to one another and secured relative to the carrier in the form of a matrix. The method includes orienting a first side of the lead matrix to be aligned with a reciprocal matrix of conductive surface pads on the area grid array semiconductor chip. First ends of the leads are electrically connected to the conductive surface pads of the area grid array chip. The second side of the lead matrix is oriented to be aligned with a reciprocal matrix of conductive surface pads on a printed wire board. Second ends of the leads of the lead matrix are electrically connected to the conductive surface pads of the printed wire board thereby establishing an electrical connection between the area grid array chip and the printed wire board.

Abstract: A multilayer package includes a plurality of interconnected large-layer-count (LLC) substrates. The LLC substrates each include conductive pads on the top and bottom surfaces of the substrate, a via in the substrate including conductive material to contact the pads on the top and bottom surfaces, and a post on a pad over the via. The posts of the substrates confront and abut each other, and are electrically bonded together. A non-flowable adhesive film mechanically bonds the LLC substrates, and has an aperture receiving the posts of the substrates.

Abstract: A method and apparatus for performing a function on an integrated circuit having a plurality of electrical contact pads is disclosed. The apparatus includes a substrate for performing the function on the integrated circuit, the substrate having a plurality of electrical contact pads and at least one electrical test contact pad. A centering housing encompasses the integrated circuit and centers the integrated circuit with respect to the substrate such that the plurality of electrical contact pads of the integrated circuit electrically connects with the plurality of electrical contact pads of the substrate. A test connector connects integrated circuit to the substrate.

Abstract: An interposer is formed by forming a laminate comprising a first sheet of electrically insulating material and a second sheet of conductive material. The first sheet has a first plurality of apertures therethrough and the second sheet is laminated to the first sheet to close the first plurality of apertures. Material is removed from the second sheet around the first plurality of apertures to form conductive pads, the pads closing the first plurality of apertures. A third sheet of electrically insulating material is attached to the second sheet. The third sheet has a second plurality of apertures therethrough, the third sheet being positioned relative to the second sheet such that the apertures of the second plurality are closed by the conductive pads. In a preferred form, the third sheet is positioned relative to the first sheet so that the apertures of the second plurality are not in registration with the apertures of the first plurality.

Abstract: A non-intrusive power control for a fault tolerant computer system which uses redundant voting at the hardware clock level. The computer includes three or more commercial central processing units (CPUs) operating synchronously. Outputs to system memory and system bus are voted by a radiation tolerant gate array which may be implemented in a custom integrated circuit. An interface control coupled to the voter can remove or connect power from a CPU and adjust CPU inputs, preventing damage to the components without terminating an operating program. The inputs and outputs at each write to and read from system memory are voted at each CPU clock cycle. A vote status and control circuit "reads" the status of the vote and controls the state of the CPUs using hardware and software. The system logic selects the best chance of recovering from a detected fault by re-synchronizing all CPUs, powering down a faulty CPU, or switching to a spare computer, resetting and re-booting the substituted CPU.

Abstract: A fault tolerant memory system having a triple bit error correction and quadruple bit error detection capability is disclosed using control logic coupled to multiple decoders each having single bit error correction/double bit error detection capabilities. The memory system can also be provided with a sparing system which provides an additional memory device to circumvent failures in individual memory devices. The memory system is suited for severe environments such as computing systems operating in outer space.

Abstract: A fault tolerant computer system is disclosed which uses redundant voting at the hardware clock level to detect and to correct single event upsets (SEU) and other random failures. In one preferred embodiment, the computer (30) includes four or more commercial processing units (CPUs) (32) operating in strict "lock-step" and whose outputs (33, 37) to system memory (46) and system bus (12) are voted by a gate array (50) which may be implemented in a custom integrated circuit (34). A custom memory controller (18) interfaces to the system memory (46) and system bus (12). The data and address (35, 37) at each write to and read from memory (46) within the computer (30) are voted at each CPU clock cycle. A vote status and control circuit (38) "reads" the status of the vote and controls the state of the CPUs using hardware and software. The majority voted signals (35) are used by the agreeing CPUs 32 to continue processing operations without interruption.

Abstract: The present invention is an apparatus and method for machining a laminate structure to form a selected shape. The method includes forming a first layer on a substrate. A first protective structure is defined that is attached to each of the first layer and the substrate. At least a portion of the protective structure has the selected shape. The laminate structure is then machined along the first protective structure thereby forming at least a portion of the selected shape.

Abstract: A digital data delivery system which uses satellite broadcasting to deliver digital data along with audio and video signals. Digital data files are divided into packets and combined with audio and video packets in a time-division-multiplexed format. The time-division-multiplexed data is digitally modulated and then uplinked to a satellite transponder. The satellite transponder broadcasts the data to a multiplicity of user stations. The data which are broadcast by the satellite transponder are received by a satellite dish at each user station. Each satellite dish then relays the data to a receiver. The receiver identifies and separates the digital data file packets from the audio and video packets and outputs the digital data file packets to a data output port. A data bridge receives the packets from the data output port, buffers the packets, and converts the packets into a format that can be read by standard commercial I/O cards.

Abstract: A method and apparatus for performing a function on an integrated circuit having a plurality of electrical contact pads is disclosed. The apparatus includes a substrate for performing the function on the integrated circuit, the substrate having a plurality of electrical contact pads and at least one electrical test contact pad. A centering housing encompasses the integrated circuit and centers the integrated circuit with respect to the substrate such that the plurality of electrical contact pads of the integrated circuit electrically connects with the plurality of electrical contact pads of the substrate. A test connector connects integrated circuit to the substrate.

Abstract: A system is provided for selectively attaching or detaching a land grid array component to a surface of circuit board where the attachment is a grid array of solid conductive solder beads or balls. A chamber contains an inert liquid, and a heater heats the inert liquid to a temperature above the melting temperature of the solder beads. A fluid level adjustment means adjusts the level of the inert liquid in the chamber between a first level below the component and a second level above the component. A first mounting means supports the circuit board above the component, and a second mounting means is positioned at least partially in the container to support the component below the circuit board and to bias the component against the circuit board. An component/board assembly is positioned in the system. The beads are uniformly melted by raising the level of the inert liquid in the chamber to above the component to permit removal of the board.