Abstract: A battery management circuit maintains voltage balance during charging and discharging of a multi-cell, series connected battery stack. The circuit prevents any cell voltage from dropping below a voltage at which degradation of the battery can start. Each of the battery connections are connected with a first polarity across one secondary winding of a transformer through a first diode and connected with a polarity opposite to the first polarity across another secondary winding of the transformer through a second diodes, where, for the cell connections corresponding to each battery except the last in the series, the secondary winding connected through the corresponding first diode is the same as the secondary winding connected through the second diode to the cell connections corresponding to the subsequent battery in the series. The circuit also provides high efficiency voltage balancing during charging of the battery stack.

Abstract: A high voltage DMOS half-bridge output for various DC to DC converters on a monolithic, junction isolated wafer is presented. A high-side lateral DMOS transistor is based on the epi extension diffusion and a five layer RESURF structure. The five layers are made possible by the epi extension diffusion which is formed by a suitable n-type dopant diffused into a p-type substrate and it is the same polarity as the epi. The five layers, starting with the p-type substrate, are the substrate, the n-type epi extension diffusion, a p-type buried layer, the n-type epi and a shallow p-type layer at the top of the epi. The epi extension is also used to shape the electric field by a specific lateral distribution and make the lateral and vertical electric fields to be the smoothest to avoid electric field induced breakdown in the silicon or oxide layers above the silicon.

Abstract: A battery management circuit maintains voltage balance during charging and discharging of a multi-cell, series connected battery stack. The circuit allows the entire energy content of the battery stack to be drained, as opposed to just monitoring the cells and turning off the discharge when the first cell voltage drops below a predetermined threshold. The circuit also provides high efficiency voltage balancing during charging of the battery stack conserving energy and keeping the temperature of the battery pack to a minimum.

Abstract: Push-pull circuits are described that are suitable for the driving of LEDs and that reduce the voltage stress on the switching transistors that is caused by the output transformer. The push-pull arrangement caters to reducing the size of the transformer as it eliminates the DC magnetic bias of the transformer core and it also caters to the integration of the semiconductor content of the circuit requiring only low side DMOS to be implemented in the monolithic, junction isolated process.

Abstract: A method and apparatus for increasing a breakdown voltage of a semiconductor device. The semiconductor device is constructed within an epitaxial tub of a first conductivity type formed within a dielectric material and comprises a surface diffusion region of a second conductivity type, opposite that of the first conductivity type, extending into the epitaxial tub, a trench surrounding and electrically isolating the epitaxial tub, a metallization line coupled to the surface diffusion traversing the semiconductor device and the trench, a first field limiting diffusion region of the second conductivity type disposed between the surface diffusion region and the trench and below the metallization line, a poly field plate positioned over the trench and beneath the metallization line, and a first contact coupled to the field limiting diffusion region, the first contact extending below the metallization line and overlapping the poly field plate.

Abstract: A method and apparatus for increasing a breakdown voltage of a semiconductor device. The semiconductor device is constructed within an epitaxial tub of a first conductivity type formed within a dielectric material and comprises a surface diffusion region of a second conductivity type, opposite that of the first conductivity type, extending into the epitaxial tub, a trench surrounding and electrically isolating the epitaxial tub, a metallization line coupled to the surface diffusion traversing the semiconductor device and the trench, a first field limiting diffusion region of the second conductivity type disposed between the surface diffusion region and the trench and below the metallization line, a poly field plate positioned over the trench and beneath the metallization line, and a first contact coupled to the field limiting diffusion region, the first contact extending below the metallization line and overlapping the poly field plate.

Abstract: A method and apparatus for increasing a breakdown voltage of a semiconductor device. The semiconductor device is constructed within an epitaxial tub of a first conductivity type formed within a dielectric material and comprises a surface diffusion region of a second conductivity type, opposite that of the first conductivity type, extending into the epitaxial tub, a trench surrounding and electrically isolating the epitaxial tub, a metal line coupled to the surface diffusion traversing the semiconductor device and the trench, a first field limiting diffusion region of the second conductivity type disposed between the surface diffusion region and the trench and below the metal line, a poly field plate positioned over the trench and beneath the metal line, and a first contact coupled to the field limiting diffusion region, the first contact extending below the metal line and overlapping the poly field plate.

Abstract: A phase converter for converting single-phase power to three-phase power, wherein the single-phase power is provided at a first and a second single-phase power terminal and the three-phase power is provided to a first, a second and a third three-phase power terminal, the phase converter comprising: a first power transfer means for coupling the first single-phase power terminal to the first three-phase power terminal; a second power transfer means for coupling the second single-phase power terminal to the second three-phase power terminal; and an inverter coupled to receive power from the first and second single-phase power terminals. The inverter provides power to the third three-phase power terminal and a neutral output by phase shifting its input power by ninety degrees.

Abstract: A method and apparatus for increasing a breakdown voltage of a semiconductor device. The semiconductor device is constructed on a semiconductor substrate including an isolation diffusion region around the semiconductor device, a substrate layer, an epi layer on top of the substrate layer, a surface diffusion region extending into the epi layer from a top surface of the epi layer and a metallization line coupled to the surface diffusion, wherein the metallization line traverses the semiconductor device and the isolation diffusion region. The semiconductor device also includes a poly field plate over the isolation diffusion region and beneath the metallization line, a field limiting diffusion region provided in the epi layer between the surface diffusion region and the isolation diffusion region and below the metallization line, and a contact coupled to the field limiting diffusion region, wherein the contact extends to a region below the metallization line and overlapping the poly field plate.

Abstract: A drive circuit that provides isolated power for gate drivers of IGBT and DMOS transistors used in inverters. The drive circuit provides power to an isolated gate driver that receives a control voltage, and in response to the control voltage, uses the power from the drive circuit to output a gate control signal that is coupled to an isolated gate bipolar transistor. The drive circuit includes a start-up circuit coupled to a supply voltage, a resonant circuit coupled to the start-up circuit and the supply voltage, and a rectifier circuit coupled to the start-up circuit and the resonant circuit, and having logic to output a power signal that is coupled to the isolated gate driver, the rectifier circuit is also coupled to the isolated gate driver at a common node.

Abstract: An improved pulse detection circuit provides for a reduced delay response and noise immunity. The pulse detection circuit includes a comparator with a biasing circuit providing first and second biasing signal states. The biasing signal states are adjustably delayed relative to the detected signal.

Abstract: A PWM inverter includes a first and a second switching transistor to generate power at an output voltage which is a function of a duty cycle of an input control signal and voltages at a positive rail and a negative rail, wherein the first switching transistor switches current from the positive rail through a first current node to an output load and the second switching transistor switches current from the negative rail through a second current node to the output load. The PWM inverter also includes a number of components to capture switching power, such as a first inductor coupled between the first current node and a first intermediate node and a second inductor coupled between the second current node and a second intermediate node, a first output inductor coupled between the first intermediate node and an output node, and a second output inductor coupled between the second intermediate node and the output node.

Abstract: An improved pulse detection circuit provides for a reduced delay response and noise immunity. The pulse detection circuit includes a comparator with a hysteresis circuit providing a hysteresis response on the order of a minimum pulse width and a reference circuit having a time constant which is a function of unexpected signal input level.