Abstract: A variable capacitance circuit enables electrostatic capacity to be adjusted as a trimmer capacitor, and that enables a temperature characteristic to be set variably. An input voltage is made to lead by a phase angle of 90° due to a differentiating circuit, before being amplified by an in phase amplifier, thus a current with phase angle of 90° shifted is obtained in such a manner as to take out the output while passing through a resistor. Gain and/or an output resistance of the amplifier are made to set variable. If a thermistor is combined with the circuit as a resistance of the differentiating circuit, temperature coefficient can be made to set variable.

Abstract: A power supply unit which has charging function enables error charging of a non-charged-type battery to be prevented, which battery is used as a power supply of an electric circuit device. Such the power supply unit is materialized with simple constitution and a low price. The power supply unit in the electric circuit device includes an external power supply connecting power supply jack, a protection circuit, and so forth. A charged-type battery case is provided with a positive electrode terminal of the power supply unit, a positive terminal corresponding to a first and a second negative electrode terminals, and a first and a second negative terminals. While a non-charged-type battery case is only provided with a positive terminal and a first negative terminal. A terminal corresponding to the second terminal is not provided for the non-charged-type battery case.

Abstract: When using an operational amplifier having a small gain-band width product, in order to obtain a circuit having deep notch characteristics, a biquad filter includes first and second stages having inverse amplifiers and third and fourth stages having inverse integrators. Replacing a feed back resistor with an impedance element provides compensation. The compensating impedance element is a reactance, such as an inductor or capacitor connected to the feed back resistor.

Abstract: In the system according to the prior invention, in order to shape the demodulated base-band signal of an FSK signal from a frequency discriminator 1 into a rectangular waveform, a waveform shaping circuit which may comprise a comparator 2 is typically provided. Any error is detected by finding a difference between the input and output signal of this comparator after the amplitudes thereof were made equal and smoothing its result. The reason why with this system the above-mentioned disadvantage occurs is that in the case of a bit synchronization signal, for example, at the point of time when its center level becomes equal to the shaping circuit output level a zero output is provided by the operation of the subtraction.

Abstract: An AFC circuit for a frequency scanning FSK receiver is so constructed that through put of data which can be transmitted is improved by shortening a header of a packet signal owing to the fact that frequency errors remaining when an object signal is caught by the frequency scanning and the frequency scanning is stopped are eliminated in a short period of time.In the frequency scanning FSK receiver having an AFC function, the scanning is stopped, when either one of upper and lower side band waves of a bit synchronizing signal of a desired signal is caught by the frequency scanning by means of a VCO, to which a scanning voltage from a scanning signal generator is applied. An operating circuit calculates a set voltage applied to the VCO at the AFC convergence to form it on the basis of a control voltage (scanning voltage) applied to the VCO at that time and a control sensitivity thereof as well as a detection voltage and a detection sensitivity of a frequency error detector at that time.

Abstract: In a frequency scanning receiver having an AFC function, when a desired signal is caught by frequency scanning due to VCO, to which a scanning voltage from a scanning signal oscillator is applied, the scanning is stopped. At this time, an operating circuit calculates to form a setting voltage of the VCO at the convergence of the AFC, based on two voltages, which are the control voltage (scanning voltage) applied to the VCO and an output voltage of a frequency error detector, and the AFC circuit is made function after having applied this setting voltage to the VCO.In this way, it is possible to shorten a header of a packet signal and to improve through-put of data, which can be transmitted, by removing a remaining frequency error in a short period of time, when the frequency scanning is stopped, by the fact that an object signal is caught by the frequency scanning.

Abstract: In a frequency discriminator for a direct conversion receiver having a simple construction, in which operations for FM demodulation by direct conversion are simplified, two-signal components I and Q, which are inphase and quadrature, respectively, in a base band, obtained by direct conversion of an FM signal by means of a local oscillator, a 90.degree. phase shifter, multipliers, LPF and AMP are amplified to a predetermined amplitude and thereafter converted into digital signals by means of A/D converters. These digital signals are given to differentiators to obtain differentials (finite differences) thereof. These values are squared by means of squarers and squares thus obtained are added by means of an adder. An output of the adder is applied to a device for extracting square root to obtain a demodulation output of the FM signal. An ROM may be used in lieu of the squares and the device for extracting square root.

Abstract: In order to reproduce a clock having little jitter in the clock reproduction in data transmission, a reproduced clock is outputted by sampling an inputted base band signal by using sampling pulses by means of a sampler and shaped by means of a flip-flop. Errors of the sampling timing are detected by sampling the base band signal two times with a predetermined interval for each bit and by comparing magnitude of fluctuations of preceding sampled values with magnitude of fluctuations of succeeding sampled values. A clock reproduced circuit acts as a phase synchronizing loop circuit during bit synchronizing signal periods, while during data signal periods errors of the sampling timing are corrected by using an output of the error detection.

Abstract: In this disclosure, a single combination of a multiplier and amplifier is utilized in a time-sharing manner for two-axis, in-phase an orthogonal phase components (I-axis and Q-axis components, respectively) so that the problem of a phase error relating to the use of the two separate circuits which are used for the respective two-axis components cannot be produced. Further, in this disclosure, this amplifier is constructed as a variable gain amplifier for the purpose of the application of AGC (automatic gain control) through the use of signal power obtained form the amplifier output, and any DC offset is automatically corrected using detecting and correcting means.

Abstract: A circuit is provided by which in the case of the transmission of a short packet signal through an FSK transmission channel having a frequency error for transmission and reception, directly from one shaped rectangular pulse of a frequency detected bit synchronization signal having a DC offset (this pulse including a bias distortion as it is) a clock signal can be generated indicating the points of time when the base-band signal passes through its center level and the point of time when it arrives its maximum or minimum value (data sampling points of time). This invention utilizes the fact that the bit synchronization signal is in the form of a sine wave because it has been band limited.

Abstract: A demodulated baseband signal of a bit synchronization signal which has been FSK modulated, because it was transmitted with a narrow frequency band, is usually in the form of a sine wave on which a DC drift is superposed. Since this DC offset will cause bias distortion for transmission codes, it is needed to detect this offset component at higher speed and with a simpler manner as soon as signal incoming occurs and to correct this. This invention attains this by providing a center error detecting circuit for an FSK signal receiver comprising: sampling means for sampling the bit synchronization signal of a demodulated FSK baseband signal by two sampling pulses separated mutually by the reciprocal of the transmission rate in bits per second; and means for finding the mean value of the two samples thus obtained, so as thereby to provide the DC center level of the baseband signal.

Abstract: A scanning radio receiver of triple conversion superheterodyne tuning, having a CPU and a keyboard. The CPU has a programmable memory to store frequencies received by the scanning radio receiver. A first and second frequency mixer for frequency converting a radio wave signal, with a respective local frequency, providing for a first and second IF signal, respectively. A PLL frequency synthesizer for generating the respective local frequencies, depending upon the frequency of the desired radio wave signal to be received, the frequency of which is keyed into the keyboard. A third frequency mixer for frequency converting the second IF signal with a third local frequency. An FM demodulator for reproducing an FM audio signal. An AM detector for reproducing an AM audio signal. An AM/FM switch for receiving the FM and AM audio signals and providing a selective audio signal in response to instruction from the CPU.

Abstract: An SSB radio receiver having an inexpensive wide-band IF filter which passes through not only a reception objective SSB station IF signal but also an interference SSB station IF signal simultaneously. These signals are SSB-detected to reproduce the original modulating audio signals with a BFO frequency, the BFO frequency itself located out of the pass-band of the wide-band IF filter. The frequency of the reception objective SSB station IF signal is selected to be nearest to the BFO frequency, preferably at an end of the pass-band width of the IF filter. Frequency spectrums of the SSB-detected audio signals are separated by a frequency difference comprising the difference between the BFO signal and the IF signals. The SSB-detected audio signals are applied to a selected low-pass filter, such as an inexpensive active filter, having a pass-band which covers or passes only the SSB-detected audio signal of the reception objective SSB station IF signal.

Abstract: A radio receiver which includes structure for direct-frequency-converting a received input signal to two axial base-band components including an in-phase base-band component and orthogonal phase base-band component. The radio receiver also includes structure for re-modulating the two axial base-band components of in-phase and orthogonal phase by using in-phase and orthogonal phase carrier waves where each carrier wave has a frequency equal to an IF signal frequency. Further, the radio receiver includes structure for composing the re-modulated components to provide the IF signal and for amplifying the IF signal, where the IF signal is an objective signal. The radio receiver further includes structure for detecting the objective signal to produce a detected output and for applying the detected output to a demodulated output terminal.

Abstract: A novel apparatus is provided for facilitating the transfer of signals from a computer for the external setting of reception frequency parameters and other operating conditions of a radio receiver having a memory which is programmable according to data in the form of an electric pulse signal. The apparatus includes an interface circuit operatively coupled between the computer and the memory of the receiver. The interface circuit converts respective signal levels of the data into the electric pulse signals enabling data transfer and communication between the computer and the memory of the receiver. An improved flat-type, reversible connector is used between the interface circuit and the receiver. The connector has upper and lower surface portions, and is operatively coupled to a receptacle in the receiver.

Abstract: A system for externally setting reception frequency parameters of a radio scanner having a memory which is programmable according to data in the form of an electric pulse signal generated according to a protocol by a computer. The system includes a computer, a stereo phone plug connected to the RS-232 port of the computer, and a scanner stereo phone jack which can receive both of the stereo phone plug and a monaural ear-phone plug. The stereo phone plug has a common electrode, a first signal electrode and a second signal electrode. The second signal electrode carries the data from the computer to the scanner. The stereo phone jack has a common electrode, a first signal electrode and a second signal electrode.

Abstract: A demodulation correcting circuit for an FSK signal receiver which include an AFC for correcting a reception frequency error to provide stabilized demodulation, said demodulation correcting circuit comprising subtracting circuit followed to a loop filter for eliminating or correcting a variation of the center frequency of the FSK modulation signal, which is caused by the fact that the AFC responds to low frequency components including DC of the FSK modulation signal and which brings about a decrease of noise margin.

Abstract: A device, which is adapted to be connected to an electronic apparatus, is capable of having a non-rechargeable battery pack or a rechargeable battery pack connected thereto. The battery packs supply a driving voltage to the electronic apparatus when connected to the device. The device can have an external power source attached thereto for energizing the electronic apparatus by a DC voltage, for disabling the driving voltage supplied by the battery packs and for supplying a charging voltage to the device and to the rechargeable battery pack. The device automatically discriminates between the rechargeable battery pack and the non-rechargeable battery pack so that the charging voltage from the external power source is only applied to the rechargeable battery pack and not to the non-rechargeable battery pack.The rechargeable battery pack includes a casing having a positive electrode and a negative electrode mounted thereon and a non-conductive insulating member which is connected to the casing.

Abstract: A multi-valued signal decoding circuit is disclosed which has a circuit for detecting a bit synchronization signal included in the multi-valued data signal transmitted in the form of a packet signal, a circuit for detecting by this detected output a timing of a transition of the bit synchronization signal, a circuit for sampling and holding the bit synchronization signal by using sampling pulses generated on the bases of said timing, and a circuit for decoding the multi-valued data signal by using decoding reference voltages formed on the basis of the sampled and held level.