Abstract: The present application provides a semiconductor structure and a manufacturing method thereof, and relates to the field of display technology. The semiconductor structure includes a substrate. The substrate includes an array region and a peripheral circuit region surrounding the array region. Multiple capacitors are arranged in an array in the array region. Virtual lines connecting centers of any three consecutively adjacent capacitors among the multiple capacitors located at an edge of the array region define a virtual angle greater than 90°.

Abstract: The present disclosure relates to the field of semiconductor circuit design, and in particular to a readout circuit layout structure and a method of reading data. The readout circuit layout structure includes: a first readout circuit structure and a second readout circuit structure having identical structures, wherein the first readout circuit structure and the second readout circuit structure each include: a first isolation module, configured to be turned on according to a first isolation signal, electrically connect a bit line and a first readout bit line, and electrically connect a complementary bit line and a first complementary readout bit line; a second isolation module, configured to be turned on according to a second isolation signal, electrically connect the first readout bit line and a second readout bit line, and electrically connect the first complementary readout bit line and a second complementary readout bit line.

Abstract: Embodiments of the present disclosure provide an alignment mark evaluation method and an alignment mark evaluation system. The alignment mark evaluation method includes: setting a process step code of a wafer with an alignment mark to be evaluated as an evaluation code; obtaining a current process step code of the wafer; if it is detected that the current process step code is the evaluation code, switching a step to be executed to an alignment mark evaluation step; and executing the alignment mark evaluation step to evaluate the alignment mark to be evaluated.

Abstract: The present disclosure provides a sense amplification circuit and a method of reading out data, including: a first PMOS transistor; a first NMOS transistor; a second PMOS transistor; a second NMOS transistor; a first control MOS transistor configured to provide a bias voltage to the first PMOS transistor according to a control signal; a second control MOS transistor configured to provide the bias voltage to the second PMOS transistor according to the control signal; a first offset cancellation MOS transistor configured to electrically connect an initial bit line to a first complementary readout bit line according to an offset cancellation signal; and a second offset cancellation MOS transistor configured to electrically connect an initial complementary bit line to a first readout bit line according to the offset cancellation signal.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip. A first conductive connection wire of the first chip is connected to a first conductive contact pad, and a second conductive connection wire of the second chip is connected to a second conductive contact pad. In addition, the first conductive contact pad includes a first conductor and a second conductor, and the second conductive contact pad includes a third conductor and a fourth conductor. The first conductor is directly opposite to the fourth conductor, and the second conductor is directly opposite to the third conductor. Therefore, pre-connection of the first conductive contact pad and the second conductive contact pad may be implemented and then the first chip and second chip that are pre-connected are transferred for bonding.