Abstract: A clock synchronization system for synchronizing a number of paging stations (24) with a system controller (23). Each paging station has a clock that includes a counter (52) that indicates the current local time and which is sequentially incremented by a counter advance signal applied thereto. A voltage controlled oscillator (58) generates the clocking signal that controls the advancement of the counter. A CPU (50) in the system controller monitors the time indicated by the counter and compares it to timing information received from a system clock. The timing information includes a time mark and a time mark send time. The system clock transmits to each paging system the time mark. At a future time, the system clock transmits the time mark send time which is the precise time at which the time mark was transmitted. The paging stations each measure the time interval between the time at which the time mark arrived and the time at which the time mark was transmitted by the system clock period.

Abstract: A method and apparatus provide an equalization time delay to synchronize a plurality of paging transmitters in a simulcast paging system. A delay equalization circuit (41 ) appropriate for use with an analog input signal includes a coder/decoder (CODEC) (50) and a digital signal processor (DSP) (58). An analog input signal is digitized or sampled by an analog-to-digital converter (ADC) in the CODEC, producing corresponding digital values that are input to the DSP. The DSP employs a selected finite impulse filter to interpolate between the sampled digital values from the CODEC to provide enhanced resolution in delaying a signal output that is output. The DSP determines a major sample index and an interpolated filter index to achieve the desired equalization time delay. These variables define two delay intervals that are combined to provide the required equalization time delay.

Abstract: An N-way power divider/combiner having isolated outputs using printed circuit board geometry that forms a ring of power resistors and output tramsmission lines spiraling around the ring to reduce the size of the circuit is disclosed. Both sides of the printed circuit board are used to achieve further size advantages. The invention thus provides a high-power radio frequency divider/combiner circuit that is much smaller than previous circuits that are able to handle equivalent power levels.

Abstract: A digital exciter (30) for selectively modulating digital or analog input data. The digital exciter includes a digital signal modulator (32) and a digital quadrature modulator (DQM)(36) comprising two digital signal processors (DSPs). The signal modulator is controlled by a control (40). An operator can selectively determine whether the digital exciter is used for modulating either two level or four level NRZ digital data and whether the device is to provide linear modulation or frequency modulation (FM) of the input signal. An interpolator (38) interpolates a 662/3 kHz timer interrupt rate used in the signal modulator to a 400 kHz rate, thereby reducing the processing load on the DSP comprising the DQM by simplifying the sine and cosine values used in the quadrature modulation. An operator can select from among a plurality of operating parameters on a menu for controlling the signal modulator, either from a local or a remote video display terminal (VDT).

Abstract: A clock synchronization system for synchronizing the performance of a number of clocks (46) so that they run parallel with a reference clock is disclosed. Each clock of this synchronization system includes a counter (52) that indicates the current time and that is sequentially incremented by a counter advance signal applied thereto. A time counter controller (54) both initializes the counter and generates the clocking signal that controls the advancement of the counter. The time counter controller further monitors the time indicated by the counter and compares it to a reference-time signal received from a reference clock. Based on the comparison, the time counter controller selectively reinitializes the counter and adjusts the rate at which the clocking signal is applied to the counter so as to ensure that the counter advances at a rate equal to the rate at which the reference clock advances.

Abstract: A method and apparatus for compensating fading and interference in a radio signal. A plurality of pilot symbols are appended to a plurality of data symbols to form successive frames that are modulated at a transmitter. The transmitted modulated signal is subject to loss of data due to simple fading and multi-path and simulcast interference. The received signals are demodulated by a receiver and processed to provide a data signal comprising the data symbols and a pilot signal comprising the pilot symbols. The data signal is delayed for sufficient time to enable channel impulse response estimates to be made of successive blocks of pilot symbols, preferably using pilot symbol blocks that both precede and follow the data symbols in the frame being processed.

Abstract: A simulcast system for broadcasting the same signal for a number of spaced-apart broadcast sites is disclosed. The system (20) of this invention includes a hub (28) adapted to receive the signal to be simulcast and a number of stations (30) that actually broadcast the signal. The hub places the digital signal packets referred to as PDBs (36). As pan of the signal packetization process, the hub evaluates the rate at which the signals should be broadcast and assigns a start time at which the signals should be broadcast; this information is attached to the PDBs. After a PDB is created it is forwarded to the stations over a link channel. Each station includes a station controller (32) and a station transmitter (34). The station controller, upon receiving a PDB, forwards the signal therein to the transmitter at the start time indicated and at the appropriate broadcast rate.

Abstract: An autoequalizing hybrid circuit for providing a cancelation path to minimize the two-wire receive path signals that are reflected onto a two-wire transmit path from a subscriber line interface circuit is disclosed. The hybrid circuit includes a variable impedance balance network. A tone generator injects a set of equalization signals into the receive path which are used to control the setting, or equalization, of the balance network. The tone generator also generates a supervisory signal into the receive path used to monitor the performance of the balance network. A detect circuit monitors the level of the reflected equalization sidetone signals and produces balance signals whenever the equalization signals fall to a null level. The detect circuit also monitors the supervisory sidetone signals and produces a recalibration signal whenever an abrupt change in the signals indicates that the balance network is no longer adequately cancelling their reflected signals.

Abstract: A telecommunications system that performs meet-me paging. The telecommunications system of this invention includes a paging system that is designed to receive calls from meet-me paging system subscribers. Once such a call is received, the system parks the call on hold while sending a page to the subscriber. The subscriber can then call the paging terminal to automatically be connected with the calling party. The system further includes a cordless telephone-2 system wherein each of the system subscribers is further provided with a portable handset from which he can access the publicly switched telephone network. Subscribers with the handset, upon receiving a meet-me page, can automatically dial the paging terminal to be connected to their calling parties. Thus, the telecommunications system of this invention provides a convenient means of providing subscribers with portable telephone service that allows them to both make outgoing calls and receive incoming calls.

Abstract: A modem for use in a simulcast paging system includes a modulator (26) and a demodulator (30), both of which produce very low jitter, enabling the modem to be used at data rates well in excess of 1,200 baud. Both the modulator and the demodulator are implemented in software using a digital signal processor (DSP) (66). The modulator initially samples a non-return-to-zero (NRZ) input at a sample rate of 19.2 KHz, interpolates transitions between logic levels, and produces a frequency shift keyed (FSK) modulated signal at a center frequency different than that used for transmitting the modulated signal. Using an interpolation timer that responds to changes in logic level on the input, the modulator changes the frequency of the FSK modulated signal at the appropriate time with much greater accuracy than would be possible without interpolation. The FSK modulated signal is filtered to substantially attenuate frequencies outside a 3 KHz bandwidth, producing a filtered signal.