Abstract: The present invention is directed to a wafer device method for processing same. A wafer for epitaxial deposition is backside sealed with a dopant seal layer (protection layer comprised of silicon dioxide or silicon nitride. Then, a layer of polysilicon is formed coextensively over the dopant seal layer. The polysilicon layer acts as a seed layer for potentially nodule forming gasses present during epitaxial deposition. During CVD epitaxy, the epitaxial layer is deposited on the primary surface with optimal resistivity uniformity. The fugitive gasses from the epitaxial process which diffuse to the wafer periphery and backside deposit as a film on the seed layer instead of in nodules. The polysilicon layer acts as a continuous seed layer which eliminates the preferential deposition at seal layer pinholes or island seed sites.

Abstract: The present invention is directed to a wafer device method for processing same. A wafer for epitaxial deposition is backside sealed with a dopant seal layer (protection layer comprised of silicon dioxide or silicon nitride. Then, a layer of polysilicon is formed coextensively over the dopant seal layer. The polysilicon layer acts as a seed layer for potentially nodule forming gasses present during epitaxial deposition. During CVD epitaxy, the epitaxial layer is deposited on the primary surface with optimal resistivity uniformity. The fugitive gasses from the epitaxial process which diffuse to the wafer periphery and backside deposit as a film on the seed layer instead of in nodules. The polysilicon layer acts as a continuous seed layer which eliminates the preferential deposition at seal layer pinholes or island seed sites.

Abstract: The present invention is directed to a built-in solution for soft error protection by forming an epitaxial layer with a graded dopant concentration. By grading a dopant concentration, starting from a first dopant concentration and ending with a second dopant concentration at the device layer, usually determined by the characteristics of the device to be built in the device layer, a constant electric field (?-field) results from the changing dopant concentration. The creation of this ?-field influences the stray, unwanted charges (or transient charges) away from critical device components. Charges that are created in the epitaxial layer are sweep downward, toward, and sometimes into, the substrate where they are absorbed, thus unable to cause a soft error in the device.

Abstract: A method for reducing microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate by post-epitaxial thermal oxidation. The method produces very smooth semiconductor wafers by performing the steps of depositing an epitaxial layer on a wafer substrate, oxidizing a top portion of the epitaxial layer, and removing the oxidized top portion. As a result, the wafer's surface presents little or no microsteps thereon.

Abstract: A system and method for monitoring a process flow of a semiconductor wafer. In one embodiment, the method initially calculates a first location of the wafer before it is processed. The wafer is then moved into a process chamber where it is processed. Then a second location of the wafer is calculated before the wafer is unloaded. If the difference between the first and second locations are within a predetermined amount, the wafer is unloaded and regular processing steps proceed. If the difference is not within the predetermined amount, an alarm is activated and the process is stopped.

Abstract: A system and method for handling post epitaxial thermal oxidation. The method produces semiconductor wafers by performing the steps of forming a wafer substrate, depositing an epilayer on the substrate, oxidizing a top portion of the epilayer, and removing the oxidized top portion. As a result, the wafer's surface is very smooth, with little or no micro-steps thereon.