Abstract: An audio communication system is disclosed. The audio communication system comprises a speaker device having at least one speaker, a first wireless communication unit and a first connector part; a dongle having control functionality, a second wireless communication unit, and a second connector part, the dangle being configured to operate in a first mode being an audio communication system pairing mode and in a second mode being an audio communication system operating mode. The second connector part is in the audio communication system pairing mode configured to interconnect with the first connector part to enable pairing of the dongle and the speaker device. The second connector part is the audio communication system operating mode configured to interconnect with an external device, providing wireless communication between the speaker device and the external device.

Abstract: The present invention relates to a microphone apparatus (30) with a main beamformer (31) that provides a main output audio signal (SM) as a beamformed signal by applying a main weight vector (BM) to a main input vector (MM). A main beamformer controller (32) repeatedly determines a main steering vector (dM) and adaptively determines the main weight vector (BM) in dependence on the main steering vector (dM) and the main input vector (MM) to increase the relative amount of voice sound (V) from the user (6) in the main output audio signal (SM).

Abstract: An earphone (1) comprising an earphone housing (2), a speaker unit (3), the speaker unit (3) comprising a diaphragm (4). A front chamber (29) is defined in the earphone between a front side (31) of the diaphragm (4) and the user (7), when the earphone (1) is worn. A rear chamber (27) is defined between the earphone housing (2) and a rear side (32) of the diaphragm (4). The earphone (1) comprises an active noise cancelling feedback microphone (9), which is arranged in the rear chamber (27) and which comprises a microphone opening (11). The diaphragm (4) comprises a cylindrical part (14), to which a voice coil (12) is attached, and an outer ring part (15) extending from the cylindrical part (14) in a direction away from a centre axis (30) of the diaphragm (4). The feedback microphone (9) is arranged farther from the centre axis (30) than the voice coil (12).

Abstract: A wireless binaural hearing device (1; 101) comprising a first earphone (2; 102), a second earphone (3; 103), a connecting device (4; 104) connecting the first earphone (2; 102) and the second earphone (3; 103) and a rechargeable battery (6). The first earphone (2; 102) comprises a first charging connector (7; 107), which is in electrical connection with the 5 rechargeable battery (6; 106), the second earphone (3; 103) comprises a second electrical connector (8; 108) which is in electrical connection with the rechargeable battery (6; 106). The hearing device (1; 101) can be a part of a system comprising a charging cradle (11; 111).

Abstract: Disclosed is an antenna structure configured to be provided in a headset to be worn. The antenna structure has a radiator and ground plate. The radiator is arranged in a first plane, and the ground plate in a second plane. The first plane, in which the radiator is arranged, is configured to be arranged substantially parallel to the surface of the head of the user, when the user wears the headset in its intended position on the head. The radiator and the ground plate are connected by a first ground connector, a second ground connector and a feed connector. The radiator has an opening between the first ground connector and the second ground connector. The opening between the first ground connector and the second ground connector provides that an object is configured to be arranged between the first plane and the second plane.

Abstract: This disclosure concerns an apparatus of multiple processors, such as microprocessors and communications therebetween and enables efficient half-duplex two-way communication between two processors, each having two logic output pins and two logic input pins, e.g. GPIO pins, available for the communication. For each of the first and the second processor (101, 102), the first logic output pin (11, 21) is connected to the second logic input pin (14, 24) of the respective other processor (101, 102), and for each of the first and the second processor (101, 102), the second logic output pin (12, 22) is connected to the first logic input pin (13, 23) of the respective other processor (101, 102).