Abstract: A positron emission tomography (PET) radiotracer for imaging lactate uptake, wherein the tracer is [18F]-3-fluoro-2-hydroxypropionic acid, or a pharmaceutical acceptable salt and/or solvate thereof. Also, a process for the radiosynthesis of [18F]-3-fluoro-2-hydroxypropionic acid, or a pharmaceutical acceptable salt and/or solvate thereof. Further, the use of [18F]-3-fluoro-2-hydroxypropionic acid, or a pharmaceutical acceptable salt and/or solvate thereof, for imaging lactate uptake in living cells, especially in humans.

Abstract: A positron emission tomography (PET) radiotracer for imaging lactate uptake, wherein the tracer is a [18F]-labelled lactate derivative. Also, a process for the radiosynthesis of the [18F]-labelled lactate derivative. Further, the use of the [18F]-labelled lactate derivative for imaging lactate uptake in living cells, especially in humans.

Abstract: A positron emission tomography (PET) radiotracer for imaging lactate uptake, wherein the tracer is a [18F]-labelled lactate derivative which is [18F]-3-fluoro-2-hydroxypropionic acid: Also, a process for the radiosynthesis of the [18F]-labelled lactate derivative. Further, the use of the [18F]-labelled lactate derivative for imaging lactate uptake in living cells, especially in humans.

Abstract: A spring bed with quick assembly and disassembly includes two cross bars, a plurality of vertical bars, a plurality of springs, and a plurality of fixing bases. The two cross bars and the vertical bars are parallel arranged with spacing. The two ends of the vertical bars are detachably assembled to the two cross bars. Each vertical bar is disposed with a plurality of fixing bases. The springs are detachably assembled to the fixing bases. Two ends of the vertical bar are detachably connected to the two cross bars.

Abstract: A spring bed with quick assembly and disassembly includes two cross bars, a plurality of vertical bars, a plurality of springs, and a plurality of fixing bases. The two cross bars and the vertical bars are parallel arranged with spacing. The two ends of the vertical bars are detachably assembled to the two cross bars. Each vertical bar is disposed with a plurality of fixing bases. The springs are detachably assembled to the fixing bases. Two ends of the vertical bar are detachably connected to the two cross bars.

Abstract: A detachable portable spring bed has a bed frame, a spring group, a cushion; the bed frame is detachable, wherein when used, the bed frame is held up, the spring is detachably assembled to the bed frame, the cushion is lay on the springs, when in packing state, the springs are detached and overlapped, the bed frame is detached to components; the spring group, the components of the bed frame, the cushion are collectively packed or independently packed. The bed frame, the spring group, the cushion are detachable.

Abstract: A non-volatile static random access memory cell and includes a bistable regenerative circuit coupled to first and second transistors and to first and second non-volatile memory cells. Methods of use include directly transferring a complementary data bit between the non-volatile memory cell and the bistable regenerative circuit. Alternatively, complementary data from the bistable regenerative circuit may be regenerated by a sense amplifier and a second bistable regenerative circuit before being transferred to non-volatile memory cells in a column of memory cells. The bistable regenerative circuit may be reset to ground potential. Applications using the non-volatile SRAM cell with direct read out from the bistable regenerative circuit include a non-volatile flip-flop or non-volatile multiplexer.

Abstract: A method and system for providing a magnetic element and a magnetic memory utilizing the magnetic element are described. The magnetic element is used in a magnetic device that includes a contact electrically coupled to the magnetic element. The method and system include providing pinned, nonmagnetic spacer, and free layers. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The method and system also include providing a perpendicular capping layer adjoining the free layer and the contact. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy in the free layer. The magnetic element is configured to allow the free layer to be switched between magnetic states when a write current is passed through the magnetic element.

Abstract: A method for determining switching characteristics in electronic devices is disclosed. The method includes applying a ramped series of electrical pulses, identifying a candidate switching pulse, grouping the measured parameter values for the remaining electrical pulses, extrapolating an expected parameter value for the candidate switching pulse for each group, and comparing the expected parameter value for each group to the parameter value for the candidate switching pulse. The method also includes applying a ramped series of electrical pulses, identifying a candidate switching pulse, and clustering the remaining measured parameter values.

Abstract: Circuit includes, in part, random access memory cells, column decoders, row decoders, and write driver circuit. Driver circuit is responsive to data and control signals. Writing data includes multiple write phases, each phase driving predetermined current through selected cell by driver setting predetermined voltages to first and second lines. Voltages are in sets such that sequential voltages of each set correspond to respective phase. During writing of first data to selected cell, driver circuit causes first signal line to be at second voltage set and second signal line to be at first voltage set. Second voltage set is greater than first voltage set. During writing of second data to selected cell, driver cause first signal line to be at third voltage set and second signal line to be at fourth voltage set. Third voltage set is smaller than the fourth voltage set.

Abstract: A method and system for providing a magnetic junction residing on a substrate and usable in a magnetic device are described. The magnetic junction includes a first pinned layer, a first nonmagnetic spacer layer having a first thickness, a free layer, a second nonmagnetic spacer layer having a second thickness greater than the first thickness, and a second pinned layer. The first nonmagnetic spacer layer resides between the pinned layer and the free layer. The first pinned layer resides between the free layer and the substrate. The second nonmagnetic spacer layer is between the free layer and the second pinned layer. Further, the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.

Abstract: A non-volatile memory (NVM) system compatible with double data rate, single data rate, or other high speed serial burst operation. The NVM system includes input and output circuits adapted to synchronously send or receive back-to-back continuous bursts of serial data at twice the frequency of any clock input. Each burst is J bits in length. The NVM system includes read and write circuits that are adapted to read or write J bits of data at a time and in parallel, for each of a multitude of parallel data paths. Data is latched such that write time is similar for each bit and is extended to the time it takes to transmit an entire burst. Consequently, the need for small and fast sensing circuits on every column of a memory array, and fast write time at twice the frequency of the fastest clock input, are relieved.

Abstract: A write circuit is adapted to provide a same logical bit to each of a multitude of memory cells for storage. Each of the multitude of memory cells stores either the bit or a complement of the bit in response to the write circuit. A read circuit is adapted to receive the bits stored in the multitude of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule. The predefined rule may be characterized by a statistical mode of the bits stored in the plurality of memory cells. Storage errors in a minority of the multitude of memory cells may be ignored at the cost of lower memory density. The predefined rule may be characterized by a first weight assigned to bits 1 and a second weight assigned to bits 0.

Abstract: A method and system for providing a magnetic substructure usable in a magnetic device, as well as a magnetic element and memory using the substructure are described. The magnetic substructure includes a plurality of ferromagnetic layers and a plurality of nonmagnetic layers. The plurality of ferromagnetic layers are interleaved with the plurality of nonmagnetic layers. The plurality of ferromagnetic layers are immiscible with and chemically stable with respect to the plurality of nonmagnetic layers. The plurality of ferromagnetic layers are substantially free of a magnetically dead layer-producing interaction with the plurality of nonmagnetic layers. Further, the plurality of nonmagnetic layers induce a perpendicular anisotropy in the plurality of ferromagnetic layers. The magnetic substructure is configured to be switchable between a plurality of stable magnetic states when a write current is passed through the magnetic substructure.

Abstract: A magnetic device including a magnetic element is described. The magnetic element includes a fixed layer having a fixed layer magnetization, a spacer layer that is nonmagnetic, and a free layer having a free layer magnetization. The free layer is changeable due to spin transfer when a write current above a threshold is passed through the first free layer. The free layer is includes low saturation magnetization materials.

Abstract: Techniques and magnetic devices associated with a magnetic element that includes a fixed layer having a fixed layer magnetization and perpendicular anisotropy, a nonmagnetic spacer layer, and a free layer having a changeable free layer magnetization and perpendicular anisotropy.

Abstract: A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers, first and second nonmagnetic spacer layers, and a free layer. The first pinned layer has a first pinned layer magnetic moment and is nonmagnetic layer-free. The first nonmagnetic spacer layer resides between the first pinned and free layers. The free layer resides between the first and second nonmagnetic spacer layers. The second pinned layer has a second pinned layer magnetic moment and is nonmagnetic layer-free. The second nonmagnetic spacer layer resides between the free and second pinned layers. The first and second pinned layer magnetic moments are antiferromagnetically coupled and self-pinned. The magnetic junction is configured to allow the free layer to be switched between stable magnetic states when a write current is passed through the magnetic junction.

Abstract: Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.