Abstract: A closed cell trench MOSFET structure having a drain region of a first conductivity type, a body of a second conductivity type, a trenched gate, and a plurality of source regions of the first conductivity type is provided. The body is located on the drain region. The trenched gate is located in the body and has at least two stripe portions and a cross portion. A bottom of the stripe portions is located in the drain region and a bottom of the cross portion is in the body. The source regions are located in the body and at least adjacent to the stripe region of the trenched gate.

Abstract: A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region.

Abstract: A fabrication method of a high cell density trench power MOSFET structure is provided. Form at least a gate trench in a silicon substrate and a gate dielectric layer on the silicon substrate. Form a gate polysilicon structure in the gate trench and cover by a passivation layer. Form a first-conductive-type body region in the silicon substrate and implant impurities with a second conductive type thereof to form a source doped region. Expose the gate polysilicon structure and the source doped region. Form a dielectric spacer having a predetermined thickness on a sidewall of the gate trench. Deposit metal on the gate polysilicon structure and the source doped region. A first and a second self-aligned silicide layer are respectively formed on the gate polysilicon structure and the source doped region. The dielectric spacer forms an appropriate distance between the first and the second self-aligned silicide layer.

Abstract: A fabrication method of a power semiconductor structure with reduced gate impedance is provided. Firstly, a polysilicon gate is formed in a substrate. Then, dopants are implanted into the substrate with the substrate being partially shielded by the polysilicon gate. Afterward, an isolation layer is formed to cover the polysilicon gate. Thereafter, a thermal drive-in process is carried out to form at least a body surrounding the polysilicon gate. Then, the isolation layer is removed to expose the polysilicon gate. Afterward, a metal layer is deposited on the dielectric layer and the polysilicon gate, and a self-aligned silicide layer is formed on the polysilicon gate by using a thermal process.

Abstract: A fabrication method of integrating a power transistor and a schottky diode on a monolithic substrate is provided. Firstly, a substrate of a first conductive type is provided. Then, at least a polysilicon gate and a second polysilicon structure are formed on the substrate. At least a portion of the second polysilicon structure is located on an upper surface of the substrate. Thereafter, a body of a second conductive type and a source region of the first conductive type are formed between the polysilicon gate and the second polysilicon structure. Then, an interlayer dielectric film is formed on the polysilicon gate to define a source contact window, but the second polysilicon structure is still exposed. Afterward, a portion of the second polysilicon structure is removed to form a schottky contact window to expose the substrate.

Abstract: A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region.

Abstract: A fabrication method of a trenched power semiconductor structure with low gate charge is provided. Firstly, a substrate is provided. Then, a gate trench is formed in the substrate. Afterward, a dielectric layer is formed on the inner surfaces of the gate trench. Then, a spacer is formed on the dielectric layer covering the sidewall of the gate trench. Thereafter, a plug structure is formed in the space at the bottom of the gate trench, which is defined by the spacer. Then, a portion of the spacer is removed with the dielectric structure and the plug structure as an etching mask. Thereafter, a portion of the dielectric layer is removed with the remained spacer as an etching mask to expose the inner surface of the upper portion of the gate trench. Afterward, with the remained spacer being kept, a gate dielectric layer is formed on the inner surface of the upper portion of the gate trench, and then a polysilicon gate is filled into the upper portion of the gate trench.

Abstract: A fabrication method of a self-aligned power semiconductor structure is provided. Firstly, a trenched polysilicon gate is formed in a silicon substrate. Then, a self-aligned polysilicon extending structure is formed on the trenched polysilicon gate. A width of the self-aligned polysilicon extending structure is smaller than that of the trenched polysilicon gate. Thereafter, the self-aligned polysilicon extending structure is oxidized to form a silicon oxide protruding structure on the trenched polysilicon gate. Then, a first spacer is formed on a sidewall of the silicon oxide protruding structure to define a source contact window.

Abstract: A power semiconductor device comprising a base, a trench, a heavily doped polysilicon structure, a polysilicon gate, a gate dielectric layer, and a heavily doped region is provided. The trench is formed in the base. The heavily doped polysilicon structure is formed in the lower portion of the trench. At least a side surface of the heavily doped polysilicon structure touches the naked base. The polysilicon gate is located in the upper portion of the trench. The gate dielectric layer is interposed between the polysilicon gate and the heavily doped polysilicon structure. The dopants in the heavily doped polysilicon structure are diffused outward to form a heavily doped region.

Abstract: A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region.

Abstract: The fabrication method of a high cell density trenched power semiconductor structure is provided. The fabrication method comprises the steps of: a) forming at least a gate trench in a substrate with a silicon oxide patterned layer formed thereon, said silicon oxide patterned layer having at least an open aligned to the gate trench; b) forming a polysilicon gate in the gate trench; c) forming a dielectric structure in the open, the dielectric structure has a sidewall thereof being lined with an etching protection layer; d) removing the silicon oxide patterned layer by selective etching; and e) forming a spacer on a side surface of the dielectric structure to define at least a contact window.

Abstract: A fabrication method of a trenched power semiconductor structure with a schottky diode is provided. Firstly, a drain region is formed in a substrate. Next, at least two gate structures are formed above the drain region, and then, a body and at least a source region are formed between the two adjacent gate structures. Thereafter, a first dielectric structure is formed on the gate structure to shield the gate structure. Then, a contact window is formed in the body and has side surface thereof adjacent to the source region to expose the source region. Afterward, a second dielectric structure is formed in the contact window. Next, by using the second dielectric structure as an etching mask, the body is etched to form a narrow trench extending to the drain region below the body. Finally, a metal layer is filled into the contact window and the narrow trench.