Abstract: The present application discloses a metering device, including a structure body of the metering device, a first metering chip and a metering master control chip. The first metering chip is configured for performing fundamental wave and full wave processing on electric energy data; the metering master control chip includes a master control chip core, a coprocessor and a storage unit, wherein the master control chip core and the coprocessor share the storage unit; and the coprocessor is configured for performing harmonic processing on the electric energy data based on the storage unit and based on a manner of instruction. By applying the solution of the present application, the electric energy data of the metering device can be processed quickly and efficiently, and a hardware cost is saved at the same time. The present application also provides an electric energy meter which has the corresponding technical effects.

Abstract: A method, an apparatus and a device for simultaneously sampling multiples signals and a medium are provided. The method includes: modulating multiple target input signals with CDM, to obtain a single target analog signal; performing ?? modulation on the single target analog signal to obtain a target digital bit stream; demodulating the target digital bit stream to obtain a target demodulated bit stream; and filtering the target demodulated bit stream to obtain multiple target output signals. With the method, the hardware overhead for simultaneous sampling of multiple-channel signals is reduced while ensuring accuracy. Accordingly, the apparatus and the device, and the medium have the above beneficial effects.

Abstract: The invention discloses a code testing method. The method includes the following steps of: acquiring a code set to be tested; loading the code set to a corresponding operating chip, and executing the code set by using the operating chip; judging whether a target code subset which is not successfully executed exists in the code set; and if yes, performing an audit testing operation on the code set. The code testing method provided by the invention is simple and feasible to apply, which improves a testing reliability and reduces a testing cost. The invention also discloses a code testing apparatus and device, and a storage medium, which have corresponding technical effects.

Abstract: The application relates to a convolutional neural network acceleration method and system based on a Cortex-M processor, and a medium. The method comprises: setting a MCR instruction and a CDP instruction according to common basic operators of a convolutional neural network, the common basic operators comprising a convolution operator, a Relu activation operator, a pooling operator, a table look-up operator and a quantization operator; and configuring an internal register of a convolutional neural network coprocessor through the MCR instruction, and then enabling the common basic operators of the convolutional neural network through the CDP instruction. Through the application, problems of inefficiency, high cost and inflexibility of a cyclic neural network algorithm in the execution of a processor are solved, and the basic operators needed for the cyclic neural network to be executed through a coprocessor instruction set are realized.

Abstract: Provided is a relaxation oscillating circuit, which comprises a charging circuit, a discharging circuit, a switch circuit, a charging-discharging capacitor and an output circuit. The charging circuit comprises a first current source and a first isolating transistor. The discharging circuit comprises a second current source and a second isolating transistor. The switch circuit comprises a main charging transistor and an auxiliary charging transistor arranged as mirror and a main discharging transistor and an auxiliary discharging transistor arranged as mirror. The main charging transistor and the main discharging transistor are alternately conducted. According to a voltage of the charging-discharging capacitor, the output circuit outputs a clock signal and a control signal.

Abstract: Provided is a relaxation oscillating circuit, which comprises a charging circuit, a discharging circuit, a switch circuit, a charging-discharging capacitor and an output circuit. The charging circuit comprises a first current source and a first isolating transistor. The discharging circuit comprises a second current source and a second isolating transistor. The switch circuit comprises a main charging transistor and an auxiliary charging transistor arranged as mirror and a main discharging transistor and an auxiliary discharging transistor arranged as mirror. The main charging transistor and the main discharging transistor are alternately conducted. According to a voltage of the charging-discharging capacitor, the output circuit outputs a clock signal and a control signal.

Abstract: The present disclosure provides a method for encryption programming, including: selecting an encrypted programming file that matches the programmer from a target folder; loading the selected encrypted programming file; if a current number of times for programming of the programmer is greater than or equal to a maximum number of times for programming, destroying the selected encrypted programming file and ending programming; otherwise, decrypting the selected encrypted programming file; if the current number of times for programming of the programmer is less than an initial number of times for programming, replacing the current number of times for programming of the programmer with the initial number of times for programming, otherwise, re-encrypting the decrypted encrypted programming file and programing the re-encrypted programming file into a target chip. A programmer is further provided.

Abstract: Disclosed is a voltage regulator, which makes a low dropout regulator stop working by controlling a sampling circuit of the low dropout regulator to break in a sleep mode, and makes an output voltage of the low dropout regulator follow an output voltage of a first bias voltage generating circuit by using a first MOS transistor connected between an voltage input end and an voltage output end of the low dropout regulator in a source follower structure, and is capable of controlling an output voltage of the whole voltage regulator by a generated bias voltage applied to the first bias voltage generating circuit by a first bias current source.

Abstract: A method, an apparatus and a device for simultaneously sampling multiples signals and a medium are provided. The method includes: modulating multiple target input signals with CDM, to obtain a single target analog signal; performing ?? modulation on the single target analog signal to obtain a target digital bit stream; demodulating the target digital bit stream to obtain a target demodulated bit stream; and filtering the target demodulated bit stream to obtain multiple target output signals. With the method, the hardware overhead for simultaneous sampling of multiple-channel signals is reduced while ensuring accuracy. Accordingly, the apparatus and the device, and the medium have the above beneficial effects.

Abstract: Disclosed are a robust method and device for estimating frequency offset in orthogonal frequency division multiplexing communication. The method includes: performing frequency-domain cyclic shift cross-correlation on preprocessed signal sequences with a short training field sequence in multiple symbol periods respectively in an initial signal receiving stage to obtain a cross-correlation result set; detecting a short training field signal according to the cross-correlation result set; when the short training field signal is detected, performing rough frequency offset estimation to obtain a rough frequency offset estimation value; performing rough frequency offset compensation according to the rough frequency offset estimation value; fixing the rough frequency offset estimation value, performing fine frequency offset estimation, and compensating residual frequency estimation; detecting a long training field signal to obtain a frame boundary; and performing channel estimation to obtain a final signal.

Abstract: Disclosed are a circuit and method for compensating frequency offset in wireless frequency shift keying communication, and belongs to the field of wireless communication technologies. The circuit includes an analog-to-digital converter, a first decimating module, a digital down-converter, a second decimating module, a frequency offset estimator, a frequency shift keying demodulator, a timing recovery module, a synchronization header detector, a frequency recovery module, a numerical-control oscillator, and a differential decoding and symbol decision module. A rough frequency offset estimation value is combined with a slicer error to generate a control signal related to frequency offset in a received signal, and the control signal is transmitted to the numerical-control oscillator to adaptively adjust a center frequency of an oscillated signal.

Abstract: The invention discloses a secure boot method for a terminal device, a terminal device and a medium, relates to the technical field of secure boot, and is used for solving a problem of low system boot security caused by lack of protection for system boot in the related art. The terminal device includes a first processor, a second processor and a shared memory. The method includes: acquiring, by the first processor, an SPL image file; acquiring, by the first processor and the second processor, a third duration and starting timing synchronously; in a case that the third duration expires, transmitting, by the first processor, the SPL image file to the second processor via the shared memory; and booting, by the first processor and/or the second processor, a system of the terminal device cooperatively based on the SPL image file received by the second processor.

Abstract: Provided are method, apparatus and device for controlling dual-mode communication, and non-transitory computer readable storage medium. The method applied to a first communication node includes: establishing a communication connection with at least one target communication node in a target communication network through a wired communication protocol, to obtain a wired communication data packet; extracting wireless communication configuration information pre-stored in the wired communication data packet; and configuring a wireless communication port based on the wireless communication configuration information.

Abstract: Disclosed are a robust method and device for estimating frequency offset in orthogonal frequency division multiplexing communication. The method includes: performing frequency-domain cyclic shift cross-correlation on preprocessed signal sequences with a short training field sequence in multiple symbol periods respectively in an initial signal receiving stage to obtain a cross-correlation result set; detecting a short training field signal according to the cross-correlation result set; when the short training field signal is detected, performing rough frequency offset estimation to obtain a rough frequency offset estimation value; performing rough frequency offset compensation according to the rough frequency offset estimation value; fixing the rough frequency offset estimation value, performing fine frequency offset estimation, and compensating residual frequency estimation; detecting a long training field signal to obtain a frame boundary; and performing channel estimation to obtain a final signal.

Abstract: Disclosed are a circuit and method for compensating frequency offset in wireless frequency shift keying communication, and belongs to the field of wireless communication technologies. The circuit includes an analog-to-digital converter, a first decimating module, a digital down-converter, a second decimating module, a frequency offset estimator, a frequency shift keying demodulator, a timing recovery module, a synchronization header detector, a frequency recovery module, a numerical-control oscillator, and a differential decoding and symbol decision module. A rough frequency offset estimation value is combined with a slicer error to generate a control signal related to frequency offset in a received signal, and the control signal is transmitted to the numerical-control oscillator to adaptively adjust a center frequency of an oscillated signal.

Abstract: Disclosed is a voltage regulator, which makes a low dropout regulator stop working by controlling a sampling circuit of the low dropout regulator to break in a sleep mode, and makes an output voltage of the low dropout regulator follow an output voltage of a first bias voltage generating circuit by using a first MOS transistor connected between an voltage input end and an voltage output end of the low dropout regulator in a source follower structure, and is capable of controlling an output voltage of the whole voltage regulator by a generated bias voltage applied to the first bias voltage generating circuit by a first bias current source.

Abstract: Provided are a method, an apparatus and a device for detecting abnormity of an energy metering chip. The method includes: inputting a target self-test signal to a to-be-tested component of a target energy metering chip in response to the target energy metering chip beginning to run under driving of a power signal; acquiring a first output signal from an output terminal of the to-be-tested component, and inputting the first output signal to a notch filter; inputting a second output signal from an output terminal of the notch filter to a signal correlator, and acquiring a third output signal from an output terminal of the signal correlator; and detecting a running state of the to-be-tested component based on the third output signal, to determine whether the target energy metering chip is abnormal.

Abstract: The present application discloses a metering device, including a structure body of the metering device, a first metering chip and a metering master control chip. The first metering chip is configured for performing fundamental wave and full wave processing on electric energy data; the metering master control chip includes a master control chip core, a coprocessor and a storage unit, wherein the master control chip core and the coprocessor share the storage unit; and the coprocessor is configured for performing harmonic processing on the electric energy data based on the storage unit and based on a manner of instruction. By applying the solution of the present application, the electric energy data of the metering device can be processed quickly and efficiently, and a hardware cost is saved at the same time. The present application also provides an electric energy meter which has the corresponding technical effects.

Abstract: A digital signal process device includes a first kernel module, configured for generating a corresponding control signal according to a DSP instruction code in a first read-only memory; a second kernel module, configured for generating a corresponding control signal according to a DSP instruction code in a second read-only memory; an arbitration module, configured for receiving a control signal corresponding to a memory access instruction and/or an arithmetic instruction sent by the first kernel module and the second kernel module, and screening out a control signal corresponding to a target memory access instruction and/or a target arithmetic instruction according to a preset priority; a data storage module, configured for receiving the control signal corresponding to the target memory access instruction sent by the arbitration module; and an arithmetic logic unit, configured for receiving the control signal corresponding to the target arithmetic instruction sent by the arbitration module.

Abstract: The invention discloses a code testing method. The method includes the following steps of: acquiring a code set to be tested; loading the code set to a corresponding operating chip, and executing the code set by using the operating chip; judging whether a target code subset which is not successfully executed exists in the code set; and if yes, performing an audit testing operation on the code set. The code testing method provided by the invention is simple and feasible to apply, which improves a testing reliability and reduces a testing cost. The invention also discloses a code testing apparatus and device, and a storage medium, which have corresponding technical effects.