Abstract: A shift register unit includes a first input/output unit which includes a first pull-down control circuit and a first auxiliary input circuit, and a second input/output unit which includes a second pull-down control circuit and a second auxiliary input circuit. The first pull-down control circuit controls a level of a first pull-down node. The first auxiliary input circuit is coupled to the first pull-down control circuit and controls the first pull-down control circuit together with a level of a first pull-up node in response to a display control signal and a blanking control signal. The second pull-down control circuit controls a level of a second pull-down node. The second auxiliary input circuit is coupled to the second pull-to down control circuit and controls the second pull-down control circuit together with a level of a second pull-up node in response to the display control signal and the blanking control signal.

Abstract: A packaging structure, a packaging method, and a display apparatus are disclosed. The packaging structure includes: a first substrate and a second substrate opposite to each other; a plurality of first sealing frames located between the first substrate and the second substrate, wherein the first substrate, the second substrate and the plurality of first sealing frames enclose a plurality of sealed cavities not communicating with each other, and each of the sealed cavities is configured to package at least one to-be-packaged unit of a to-be-packaged device; and a first filler located in the sealed cavity.

Abstract: A display panel, a display device, and a drive method are provided. The display panel includes a plurality of sub-pixel units arranged in an array and a gate drive circuit, and the array includes N rows. The gate drive circuit includes a plurality of cascaded shift register units and N+1 output terminals arranged in sequence, each of the plurality of cascaded shift register units is configured to output a gate scan signal for driving at least two rows of sub-pixel units in the N rows of the array to work; pixel drive circuits of an (n)-th row of sub-pixel units are connected to an (n)-th output terminal of the gate drive circuit to receive the gate scan signal as a scan drive signal, and sensing circuits of the (n)-th row of sub-pixel units are connected to an (n+1)-th output terminal of the gate drive circuit.

Abstract: The present disclosure discloses a shift register, a gate driving circuit and a display device. The shift register includes a display pre-charge reset circuit, a sensing cascade circuit, a sensing pre-charge reset circuit, a pull-down control circuit and an output circuit, where the display pre-charge reset circuit, the sensing cascade circuit and the sensing pre-charge reset circuit share the same pull-down control circuit and the same output circuit, the output circuit is coupled to at least one signal output terminal, the output circuit includes output sub-circuits in one-to-one correspondence with the at least one signal output terminal, and each output sub-circuit is configured to write a driving clock signal into the corresponding signal output terminal in a display output stage and a sensing output stage in response to a control of a voltage of a pull-up node in an effective level state.

Abstract: The present disclosure relates to the field of display technology and, in particular, to a gate driving structure, an array substrate, and a display device. The gate driving structure may include: a base substrate; a shift register formed on the base substrate, and including a plurality of thin film transistors and at least one capacitor, the capacitor being coupled to the thin film transistor; and a signal wiring group formed on the base substrate, and including a plurality of signal wirings spaced apart from each other, the signal wiring being coupled to the thin film transistor. An orthographic projection of the capacitor on the base substrate is at least partially overlapped with an orthographic projection of the signal wiring group on the base substrate.

Abstract: The present disclosure provides display apparatuses, gate drive circuits, shift register units and driving methods thereof. The shift register unit includes: an outputting module, configured to output a composite output signal under a control of a potential of a pull-up node; a pull-up module, configured to charge the pull-up node under a control of a display control signal terminal and charge the pull-up node under a control of a potential of a black insertion node; a first reset circuit configured to, under a control of the reset signal terminal and the potential of the black insertion node, control a voltage control node to communicate with the pull-up node; a current-limiting circuit, connected between the voltage control node and a first voltage terminal; and a charging module, configured to charge the voltage control node under the control of the potential of the pull-up node.

Abstract: A pixel driving circuit, a display device and an electronic device are provided. The pixel driving circuit includes: a first sub-pixel driving circuit, a second sub-pixel driving circuit, a third sub-pixel driving circuit, and a fourth sub-pixel driving circuit sequentially arranged in a first direction; a detection line; a first power line extending in the second direction; and a second power line extending in the second direction, wherein one of the first power line and the second power line is provided on a side of the second sub-pixel driving circuit away from the third sub-pixel driving circuit, and the other of the first power line and the second power line is provided on a side of the third sub-pixel driving circuit away from the second sub-pixel driving circuit.

Abstract: A shift register, a gate driving circuit and a gate driving method are provided. The shift register includes: a display pre-charging reset circuit, a display noise reduction circuit and an output circuit, the output circuit is provided with at least one signal output terminal, and includes at least one output sub-circuit; the display pre-charging reset circuit is configured to write a first scanning voltage into a pull-up node in response to a control of a first signal input terminal; and write a second scanning voltage into the pull-up node in response to a control of a second signal input terminal; the display noise reduction circuit is configured to write the second scanning voltage into a pull-down node in response to the control of the first signal input terminal; and write the first scanning voltage into the pull-down node in response to the control of the second signal input terminal.

Abstract: A display substrate and a manufacturing method thereof, and a display panel are provided. The display substrate includes a base substrate having a display region and a peripheral region adjacent to the display region, the peripheral region being provided therein with a gate driver-on-array circuit including a plurality of transistors and capacitors, all of the transistors are provided in a transistor region, at least a part of the plurality of capacitors are provided in a capacitor region, and the capacitor region is located on a side of the transistor region distal to the display region; and an encapsulation structure for encapsulating the display region and the transistor region together; the peripheral region further including a sealing region for arranging a sealing structure therein, the capacitor region is located in the sealing region, and the sealing region is provided on a side of the encapsulation structure distal to the display region.

Abstract: A shift register circuit includes a first input sub-circuit, an output sub-circuit and an output control sub-circuit. The first input sub-circuit transmits a signal received at a second signal input terminal to a pull-up node. The output sub-circuit transmits a signal received at a first clock signal terminal to a shift signal output terminal, and transmits a signal received at an output signal transmission terminal to a first scan signal output terminal. The output control sub-circuit transmits a signal received at a chamfering signal terminal to the first scan signal output terminal in a predetermined time before the first scan signal output terminal stops outputting the signal from the output signal transmission terminal. The chamfering signal terminal transmits a signal with a voltage amplitude within a variation range of a voltage amplitude of a signal of the first scan signal output terminal.

Abstract: A packaging method of a display panel, the packaging method including: defining, on a cover plate, at least one adhesive coating region that each is to cover a respective target specially-shaped pattern and have a regular shape; forming a packaging adhesive in the at least one adhesive coating region; bonding the cover plate formed with the packaging adhesive with a substrate formed with at least one target specially-shaped pattern, so that a display region of each target specially-shaped pattern is located within a respective adhesive coating region; and cutting the substrate and the cover plate that have been bonded according to the target specially-shaped pattern to obtain the display panel.

Abstract: A shift register driving method includes: in a black insertion driving period, the black insertion input circuit, in response to a black insertion control signal, causing the output circuit to first output a first sense driving signal and a second sense driving signal, so that the control electrode of the switching transistor receives the first sense driving signal to turn on the switching transistor, the first electrode of the switching transistor receives a sensing data signal, and the control electrode of the sensing transistor receives the second sense driving signal to turn on the sensing transistor, and a second electrode of the sensing transistor outputs a pixel compensation signal, at the same time the sub-pixel stops emitting light; the output circuit outputs a black insertion driving signal, and the pixel circuit receives the black insertion driving signal to turn off the driving transistor, and the sub-pixel keeps not emitting light.

Abstract: A pixel driving circuit includes a light-emitting control sub-circuit and a plurality of display control sub-circuits. The light-emitting control sub-circuit is connected to a light-emitting control signal terminal, a power supply signal terminal and a light-emitting control node, and is configured to transmit a power supply signal from the power supply signal terminal to the light-emitting control node in response to a light-emitting control signal received from the light-emitting control signal terminal. Each display control sub-circuit is connected to the light-emitting control node, a scan signal terminal, a data signal terminal, and a light-emitting element. Each display control sub-circuit is configured to, in response to a scan signal received from the scan signal terminal, output a driving signal according to the power supply signal and a data signal from the data signal terminal, so as to drive the light-emitting element to emit light.

Abstract: A gate driving unit includes an Nth stage of shift register unit and an (N+1)th stage of shift register unit, N is a positive integer. The Nth stage of shift register unit includes an Nth stage of pull-up node control circuit, and the (N+1)th stage of shift register unit includes an (N+1)th stage of pull-up node control circuit. The Nth stage of pull-up node control circuit is electrically connected to an Nth stage of pull-up node and a control line, controls a potential of the Nth stage of pull-up node under the control of a control signal inputted by the control line. The (N+1)th stage of pull-up node control circuit is electrically connected to an (N+1)th stage of pull-up node and the control line, respectively, and controls a potential of the (N+1)th stage of pull-up node under the control of the control signal inputted by the control line.

Abstract: The present disclosure relates to a gate drive circuit. The gate drive circuit includes: cascaded GOA units, first clock signal lines, second clock signal lines, connecting lines and electrostatic protection sub-circuits. The first clock signal lines are used to provide various clock signals to the GOA units. The second clock signal lines are used to, when any of the clock signal lines is broken, replace the broken clock signal line to transmit a corresponding clock signal. The electrostatic protection sub-circuits are electrically connected to corresponding first clock signal lines or corresponding second clock signal lines through the connecting lines. Orthographic projections of the connecting lines on a plane where corresponding first clock signal lines or corresponding second clock signal lines are located intersect with the corresponding first clock signal lines and the corresponding second clock signal lines, respectively.

Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, and a GOA circuit, a source electrode IC and PLG wires arranged on the base substrate, and the PLG wires connect the GOA circuit with the source electrode IC. The GOA circuit transmits a GOA signal, and the GOA signal comprises a cascade signal and a non-cascade signal. The PLG wires comprise a first PLG wire group and at least one second PLG wire group, the first PLG wire group transmits the cascade signal, the second PLG wire group transmits the non-cascade signal, a line width of the first PLG wire group is smaller than that of the second PLG wire group, and the first PLG wire group is located at a side of the second PLG wire group distal to an active area of the base substrate.

Abstract: A shift register circuit is provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a first control sub-circuit and a second control sub-circuit. The input sub-circuit is connected to a first signal input terminal, a second signal input terminal and a first node. The output sub-circuit is connected to the first node, a first clock signal terminal and a first output terminal. The first control sub-circuit is connected to a first power supply voltage terminal, a second power supply voltage terminal, the first node and a second node. The second control sub-circuit is connected to the second power supply voltage terminal, a third power supply voltage terminal, the second node and a third node, and the third node is further connected to the input sub-circuit.

Abstract: A pixel circuit includes: a first driving line, a second driving line, a data line, and a sensing line; a first pixel sub-circuit including a first writing unit, a first sensing unit, and a first driving unit, the first driving unit being configured to drive a first light-emitting unit to emit light; and a second pixel sub-circuit including a second writing unit, a second sensing unit, and a second driving unit, the second driving unit being configured to drive a second light-emitting unit to emit light. The first writing unit and the second sensing unit are connected to the first driving line, so as to be turned on or off synchronously under control of the first driving line. The second writing unit and the first sensing unit are connected to the second driving line, so as to be turned on or off synchronously under control of the second driving line.

Abstract: A pixel driving circuit includes: a data writing sub-circuit configured to write a data signal received at a data signal terminal into a first node under control of a first scanning signal received at a first scanning signal terminal; a driving sub-circuit configured to drive a light-emitting device coupled to a second node to work under control of a voltage of the first node and a first power supply voltage signal received at a first power supply voltage signal terminal; and a time control sub-circuit configured to transmit a control signal received at a control signal terminal to the first node under control of a second scanning signal received at a second scanning signal terminal after the light-emitting to device works for a preset time, so that the driving sub-circuit is turned off to control the light-emitting device to stop working.

Abstract: A gate driving unit, a circuit, a display substrate, a display panel, and a display device are provided. The gate driving unit includes an Nth stage of shift register unit and an (N+1)th stage of shift register unit, N is a positive integer. The Nth stage of shift register unit includes an Nth stage of pull-up node control circuit, and the (N+1)th stage of shift register unit includes an (N+1)th stage of pull-up node control circuit. The Nth stage of pull-up node control circuit is electrically connected to an Nth stage of pull-up node and a control line, respectively, is configured to control a potential of the Nth stage of pull-up node under the control of a control signal inputted by the control line. The (N+1)th stage of pull-up node control circuit is electrically connected to an (N+1)th stage of pull-up node and the control line, respectively, and is configured to control a potential of the (N+1)th stage of pull-up node under the control of the control signal inputted by the control line.