Abstract: A manufacturing method for a chip packaging structure, comprising: arranging a metal heat dissipation layer on a substrate comprising at least one flange on its side surface; forming a sealing pin located on an upper surface of the flange, so that the metal heat dissipation layer, the flange and the sealing pin form a cavity for accommodating an encapsulant; attaching a chip structure on an upper surface of the metal heat dissipation layer using an adhesive layer; forming the encapsulant encapsulating an upper surface of the substrate, the metal heat dissipation layer and the chip structure, the sealing pin extends to a periphery of the upper surface of the encapsulant; performing a mechanical or chemical treatment, to make electrode connecting structures on an upper layer of the chip structure exposed outside the first encapsulant; arranging a pin layer for electrically coupling to and covering the electrode connection structures.

Abstract: Disclosed a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises: a metal heat dissipation layer; a chip structure comprising a plurality of first electrical contacts on an upper surface of the chip structure; a pin layer comprising a plurality of second electrical contacts and a plurality of separate metal bumps; an encapsulant encapsulating at least one portion of the chip structure, the metal heat dissipation layer and the pin layer, wherein at least one portion of the pin layer is exposed to an upper surface of the encapsulant, and an lower surface of the metal heat dissipation layer is exposed outside the encapsulant. The metal heat dissipation layer includes a flange on the side surface for tightly combining the metal heat dissipation layer and the encapsulant.