Patents Assigned to Hewlett-Packard Development, L.P.
  • Patent number: 6618258
    Abstract: Portable memory storage cards can be stacked together in a receiver that also serves as a player, allowing for compact and efficient storage and usage of those cards. The portable memory storage cards have at least one contact on both sides, positioned such that the cards are reversible. A receiver for the cards also serves as the player. A set of contacts is provided at one end of a storage cavity, into which an arbitrarily large number of cards may be stacked together, such that their contacts touch to form a bus. The stacked cards are biased against the set of contacts to establish physical contact between the set of contacts in the storage cavity and contacts on the adjacent card. The cards each include at least one alignment guide to restrict the motion of adjacent cards relative to one another when cards are stored in the cavity of the receiver.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: September 9, 2003
    Assignee: Hewlett-Packard Development, L.P.
    Inventor: Andrew C Goris
  • Patent number: 6597692
    Abstract: The present invention provides a new crossbar switch which is implemented by a plurality of parallel chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-day technology limits of about one thousand I/O pins) although conventional systems typically support no more than 32 nodes. The crossbar switch can be implemented to support only one node, then one chip can be used to route all 64 bits in parallel for 64 bit microprocessors.
    Type: Grant
    Filed: April 21, 1999
    Date of Patent: July 22, 2003
    Assignee: Hewlett-Packard Development, L.P.
    Inventor: Padmanabha I. Venkitakrishnan
  • Patent number: 6567960
    Abstract: An RLC module is configured to provide a simplified circuit modeling of a selected circuit net (or portion) of an electronic circuit. The RLC module may be configured to substitute an RLC circuit model for the selected circuit net, where the effective values of the capacitance and inductance for the RLC circuit model are retrieved from a table of capacitance and inductance values. A set of interconnect geometry factors (e.g., line length, line width, driver/receiver length, etc.) that describes the circuit net is used as an index into the table of capacitance and inductance values. The retrieved values of the effective capacitance and inductances values may be used to calculate a delay for the RLC circuit model. The RLC module may provide the capability to quickly calculate a delay for a selected circuit net without using computationally intensive calculations for inductance and capacitance values of circuit nets.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: May 20, 2003
    Assignee: Hewlett-Packard Development L.P.
    Inventors: Norman Chang, Yu Cao, Osamu Samuel Nakagawa, Shen Lin, Weize Xie