Abstract: An IC tag inlet (100) is configured by: an upper side antenna (102) and a lower side antenna (103) sandwiching a semiconductor chip (101) that includes an upper electrode (132) and a lower electrode (133) from both upper and lower directions; and a support resin (104) covering the semiconductor chip (101). The semiconductor chip (101) is a micro chip having an outer size of 0.15 mm square or smaller, and a thickness of 10 ?m or smaller. In a manufacturing process of the IC tag inlet (100), in order to make the handling of the semiconductor chip (101) easy, prior to a step of sandwiching the semiconductor chip (101) between the upper side antenna (102) and the lower side antenna (103), the whole surface of the semiconductor chip (101) is covered by the support resin (104), so that an effective volume is made large.

Abstract: A plasma display device includes a plasma display panel provided with plural discharge cells each having discharge gas, a pair of sustain electrodes which generate sustain discharge, and a phosphor, and a driving circuit which applies a sustain pulse voltage between the pair of sustain electrodes for generating the sustain discharge. The sustain pulse voltage is formed of a first portion having a main portion of a first voltage Vp and a second portion succeeding the first portion in time and having a main portion of a second voltage Vs higher than the first voltage Vp, the sustain discharge is formed of a pre-discharge and a main discharge succeeding the pre-discharge in time, and the first voltage Vp is selected to satisfy Vpmin?Vp<Vs, where Vpmin is a minimum of the first voltage Vp which stabilizes the sustain discharge.

Abstract: Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.