Abstract: A method for separating luminance and chrominance of a composite TV analog signal includes the steps of: measuring first differences between horizontal neighbor pixels, second differences between vertical neighbor pixels and third differences between temporal neighbor pixels encoded in the composite TV analog signal; comparing the first, second and third differences with one another to obtain a minimum difference used as a factor of a weighting function; and filtering the composite TV analog signal simultaneously by a two-dimensional (2D) comb filter and a three-dimensional (3D) comb filter according to the weighting function on the basis of the minimum difference to obtain a luminance signal and a chrominance signal, in which magnitudes of a part of the composite TV analog signal filtered by the 2D comb filter and magnitudes of the other part of the composite TV analog signal filtered by the 3D comb filter are determined by the weighting function.

Abstract: A receiver apparatus can identify a plurality of patterns corresponding to scrambled synchronization bytes of a transport stream in a number of successive signal frames containing FEC code blocks, determine a pattern distribution into which most of the patterns identified in the successive signal frames map, and generate a synchronization signal locked to a distribution of the FEC code blocks associated with the pattern distribution. With this synchronization signal, FEC code blocks can be timely handled in a reliable manner through a FEC decoder, making the receiver apparatus more efficient and robust. In other embodiments, methods of handling FEC code blocks in a receiver apparatus are also described.

Abstract: A receiver apparatus comprises a LDPC decoder that can apply an accelerated belief propagation method for iteratively decoding each code block. When the number of iterations reaches a certain threshold value, the accelerated belief propagation method can adjust the initial condition used in each iteration. The initial condition is adjusted so as to enhance the likelihood of convergence in the iterative method. As a result, performance of the decoder and receiver apparatus can be improved.

Abstract: A system and method of correcting baseline wander (BLW) are disclosed. An analog-to-digital converter (ADC) converts an analog input to a digital output, and a slicer maps the digital output to one of a plurality of predefined values. A BLW correction unit generates a BLW correction value according to a difference between an input and an output of the slicer. A correction controller generates a fine correction value and a coarse correction value according to the BLW correction value. Specifically, the fine correction value is used to correct the digital output of the ADC, and the coarse correction value is used to correct the analog input of the ADC.

Abstract: A method of converting a frame rate of a video signal includes the steps of: receiving a pulldown film sequence existing in or converted from a sequence of successive-in-time frames of the video signal, in which the pulldown film sequence comprises a plurality of diverse original frames each having a corresponding number of duplicate frames; modifying the original frames; performing estimation of at least one motion vector associated with the modified original frames; and interpolating new frames between the modified original frames in accordance with the motion vector.

Abstract: A transceiver having HEAC and Ethernet connections is disclosed. An active hybrid & common-mode bias (AHCB) unit facilitates the transmission of differential transmission signals and the reception of first differential reception signals. An Ethernet line gate controllably configures the pairing among first and second differential Ethernet signals, the differential transmission signals and second differential reception signals. An Ethernet physical-layer (PHY) transceiving unit receives both or one of the first and second differential reception signals and the differential transmission signals, followed by processing the reception signals at a physical layer.

Abstract: A method is used for compensating a boundary of an image, in which each scan line in the image is shifted by a corresponding line shift amount. The method determines a boundary region for the image and moves each pixel in a scan line from an original position to a new position within the boundary region, in which the new position is determined according to the width of the boundary region, the original position, and a line shift amount, and the scan line is shifted by the line shift amount. Then, the method interpolates at least one pixel into the scan line according to the moved pixels for generating a compensated image.

Abstract: A system and method of correcting baseline wander (BLW) are disclosed. An analog-to-digital converter (ADC) converts an analog input to a digital output, and a slicer maps the digital output to one of a plurality of predefined values. A BLW correction unit generates a BLW correction value according to a difference between an input and an output of the slicer. A correction controller generates a fine correction value and a coarse correction value according to the BLW correction value. Specifically, the fine correction value is used to correct the digital output of the ADC, and the coarse correction value is used to correct the analog input of the ADC.

Abstract: The invention is directed to a system and method of regulating a slicer for a communication receiver. A zero-crossing accumulator receives a slicer output from the slicer and accordingly determines a zero-crossing length of the slicer output. A threshold decision unit regulates at least one threshold value of the slicer according to the zero-crossing length.

Abstract: An overdrive system adaptable for a dynamic gamma generator is disclosed. A current gray-to-voltage converter (G/V) converts image data of a current frame from gray code to voltage level, and a previous gray-to-voltage converter (G/V) converts image data of a previous frame from gray code to voltage level. The voltage level of current frame and the voltage level of previous frame are inputted to an overdrive-voltage lookup table to retrieve an overdrive voltage level. Afterwards, a voltage-to-gray converter (V/G) converts the retrieved overdrive voltage level from voltage level back to gray code, resulting in an overdrive gray code. Accordingly, the overdrive gray code is compensated. Alternatively, the overdrive gray code is used to update an overdrive-gray-code lookup table, an output gray code of which is fed to the source driver.

Abstract: An image display system including an adjuster, a first analysis module, a second analysis module and a brightness compensation module is disclosed. The adjuster utilizes a specific method and a depth information to adjust a processed image to generate a first image and a second image. The first analysis module analyzes the first image to obtain a first image distribution result. The second analysis module analyzes the second image to obtain a second image distribution result. The brightness compensation module adjusts brightness of the first and the second images according to the first and the second image distribution results. The adjusted first image serves as a left-eye image component and the adjusted second image serves as a right-eye image component.

Abstract: A digital demodulator adapted in a receiver and a digital demodulation method are provided. The digital demodulator includes: a phase splitter, a complex multiplier, an AFC, a limiter, a phase detector, a re-tracker, a post-multiplier and an oscillator. The phase splitter generates a complex signal from the input signal. The complex multiplier multiplies the complex signal by both first and second phase signals to generate first and second base band signals. The AFC generates a first output signal. The limiter generates a trend signal and the re-tracker generates a tuning signal from the first output signal. The phase detector multiplies the trend and second base signal and adjusts the multiplied signal based on the tuning signal. The oscillator generates the first and second phase signals according to the output of the phase detector. The post-multiplier multiplies the trend signal by the first and second base band signals for output.

Abstract: A signal processing device with high efficiency of teletext information processing is provided. The signal processing device is configured to receive and encode a transport stream for display, wherein the transport stream provides teletext information associated with a plurality of teletext lines and video information associated with a plurality of video lines. The video signal processing device includes a memory configured to store line enable signals and line data associated with the teletext lines and the video lines, a VBI controller coupled to the memory, configured to read the memory to obtain the line data associated with enabled teletext lines of the teletext lines, and an TV encoder coupled to the VBI controller, configured to receive and encode the line data associated with the enabled teletext lines for display.

Abstract: A digital receiver includes an analog front-end circuit, an automatic-gain controller, a compensation circuit, and a demodulator. The analog front-end circuit receives an input signal, adjusts an average amplitude of the input signal, and converts the adjusted input signal to generate a digital signal according to a control signal. The automatic-gain controller is coupled to the analog front-end circuit for generating the control signal feedback to the analog front-end circuit according to the digital signal. The compensation circuit is coupled to the analog front-end circuit for detecting an average amplitude of the digital signal to generate a detecting result and for determining whether to compensate the average amplitude of the digital signal to generate a compensated digital signal according to the detecting result. The demodulator is coupled to the compensation circuit for demodulating the compensated digital signal to generate an output signal.

Abstract: A method and system of automatically correcting a sampling clock in a digital video system are disclosed. Sampling clocks with different phases are generated and subjected in turn to analog-to-digital conversion (ADC). A difference of at least a pair of neighboring data out of the ADC with respect to each phase is determined. A maximum difference is determined, and the sampling clock with the phase corresponding to the maximum difference is thus generated.

Abstract: A carrier recovery apparatus includes a pilot strength detector, a first lock loop, a second lock loop, and a controller. The pilot strength detector determines whether a pilot strength of an input signal is greater than a threshold value to generate a control signal. The first lock loop performs a first carrier recovery on the input signal. The second lock loop performs a second carrier recovery on the input signal. The controller selectively allows the first lock loop to perform the first carrier recovery on the input signal or the second lock loop to perform the second carrier recovery on the input signal according to the control signal. The first lock loop is a pilot-based FPLL and the second locked loop is a pilot-less PLL.

Abstract: A system and method of enhancing depth of a three-dimensional (3D) image are disclosed. A depth generator generates at least one depth map associated with an image. A depth enhancer enhances the depth map by stretching a depth histogram associated with the depth map, wherein the depth histogram is a distribution of depth levels of pixels of the image.

Abstract: Circuits for performing motion estimation (ME) and motion compensation (MC) are disclosed. In the ME circuit, rows of a first register are correspondingly coupled to rows of a first memory that stores a search range of a first frame, and rows of a second register are correspondingly coupled to rows of a second memory that stores a search range of a second frame. Block-matching metric calculations are performed through the search range to obtain a motion vector (MV). In the MC circuit, first multiplexers couples each row of a first register to corresponding row of a first memory, and each macro block (MB) may accordingly be selected from the first memory and loaded into the first register. Second multiplexers couples each row of a second register to corresponding row of a second memory, and each MB may accordingly be selected from the second memory and loaded into the second register.

Abstract: A interconnect structure includes a substrate, a pair of interconnect pads, a pair of transmission lines. The substrate is stacked with at least one layer, and each of the layers has a first surface plane and a second surface plane. The pair of interconnect pads are formed on a first surface plane of a first layer of the substrate. The pair of transmission lines is formed on the first surface plane of the first layer, and the pair of transmission lines have a Y-type close trace portion for connection to the pair of interconnect pads. Further, the first surface plane of the layer is formed with a via hole which is formed within a groin region defined by the Y-type close trace portion and extends to a second surface plane of the first layer, wherein the second surface of the first layer is a power plane or a ground plane.

Abstract: A receiver with capability of correcting error is disclosed. A soft slicer generates quantized data and associated soft data. A decoder with error recovery generates decoded quantized data and a soft sequence, and is capable of correcting one bit of the quantized data. A serial-to-parallel (S/P) converter with code corrector generates parallel data, and is capable of correcting two bits of de-scrambled data bits.