Patents Assigned to Hitachi Europe, Ltd.
  • Patent number: 6895025
    Abstract: An optical switching apparatus comprises an optically resonant system (3, 12) and a pulse source configuration (1, 2) to direct first and second pulses (P1, P2) of optical radiation into the resonant system, the first pulse (P1) being configured to produce a coherent excitation of the resonant optical system so as to change its optical characteristics and the second pulse (P2) being of a phase to thereafter de-excite the coherent excitation produced by the first pulse. According to the invention, a device (13, 34) driveable externally of the resonant system such as an optical amplifier or a laser, maintains the coherence of the excitation produced by the first pulse until de-excited by the second pulse. The optically resonant system may comprise an optically responsive medium (3) which is capable of being switched into a state of coherent resonance or a resonant cavity.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: May 17, 2005
    Assignee: Hitachi Europe, Ltd.
    Inventors: Albert Herble, Jeremy Allam
  • Patent number: 6771012
    Abstract: Apparatus for producing a flux of charge carriers that may be used in many applications including imaging and lithography comprises an electron source which includes an emitter with a tip radius of about one nanometer and a closely configured extractor, together with a specimen for receiving an electron beam from the source. The apparatus may operate in air under atmospheric conditions and at a much reduced operating voltage.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: August 3, 2004
    Assignee: Hitachi Europe, Ltd.
    Inventors: Haroon Ahmed, David Hasko, Alex Driskill-Smith, David Arfon Williams
  • Patent number: 6574143
    Abstract: A flash memory cell is based on a floating gate transistor design in which a floating gate is separated from a channel by a tunnel oxide. The cell is programmed and erased by electrons tunnelling on and off the floating gate through the tunnel oxide. To retain charge stored on the floating gate, the tunnel oxide is relatively thick. As a result it takes a long time, of the order of 100 &mgr;s, to program and erase the cell, Injection of charge onto the floating gate is helped by hot-electron and channel inversion effects. However, no such effects help tunnelling of charge off the floating gate, Introduction of a silicon heterostructure hot-electron diode comprising an intrinsic silicon region promotes electron transport from the floating gate during erasing cycles and so reduces the erase voltage. Furthermore, the intrinsic silicon region provides an additional barrier to charge leakage, so permitting a thinner tunnel oxide to be used and thus read/write cycles become shorter.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 3, 2003
    Assignee: Hitachi Europe, Ltd.
    Inventor: Kazuo Nakazato