Patents Assigned to Hitachi Limited
  • Publication number: 20160218543
    Abstract: The electric power loss at the time of charging/discharging storage batteries is reduced. An electric power system control device maintains a balance of power supply and demand of an electric power system by controlling charging/discharging of a storage battery, and includes a frequency detection unit; a frequency prediction unit which predicts the frequency from the frequency calculated by the frequency detection unit and history data of power generation/load supply-demand data. A charging/discharging amount determination unit sets a charging/discharging amount corresponding to a value lower or higher than the frequency of the electric power system predicted by the frequency prediction unit within a range not exceeding a lower or higher limit value of the frequency and determines the charging/discharging amount of the storage battery based on the value. And, a control command unit transmits a control command to the storage battery based on a result of the charging/discharging amount determination unit.
    Type: Application
    Filed: September 27, 2013
    Publication date: July 28, 2016
    Applicant: Hitachi, Limited
    Inventors: Takaharu ISHIDA, Shinsuke ANDOH, Hiroki SATOH, Hideyuki KOBAYASHI, Kazuya SHOJIKI
  • Patent number: 8128796
    Abstract: It is an object of this invention to measure small amounts of a plurality of sample solutions at the same time. The small amounts of sample solutions are respectively placed on measuring electrodes, a medium is placed across the plurality of sample solutions, a liquid joint of a reference electrode is brought into contact with the medium, and a potential difference between each of the measuring electrodes and the reference electrode via the medium is measured.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: March 6, 2012
    Assignee: Hitachi, Limited
    Inventors: Yu Ishige, Masao Kamahori
  • Patent number: 7893426
    Abstract: A single-electron transistor (1) has an elongate conductive channel (2) and a side gate (3) formed in a 5 nm-thick layer (4) of Ga0.98Mn0.02As. The single-electron transistor (1) is operable, in a first mode, as a transistor and, in a second mode, as non-volatile memory.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: February 22, 2011
    Assignee: Hitachi Limited
    Inventors: Jörg Wunderlich, David Williams, Tomas Jungwirth, Andrew Irvine, Bryan Gallagher
  • Patent number: 7855698
    Abstract: A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of sub fields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SF1 through SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N+1 gradation levels from a luminance level 0 to a luminance level N.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: December 21, 2010
    Assignee: Hitachi Limited
    Inventors: Yukio Otobe, Masahiro Yoshida, Nobuaki Otaka, Masaya Tajima, Katsuhiro Ishida, Kiyotaka Ogawa, Toshio Ueda
  • Patent number: 7530305
    Abstract: The present invention provides a new and highly reliable substrate manufacturing technology for manufacturing a substrate with a protrusion pattern, which can decrease structural defects caused by involving bubbles when the protrusion pattern is formed, can improve the reliability of the product and the yield of the product, does not require off-line steps such as vacuum deaeration, and therefore improves the production efficiency and simplifies the steps. According to the present invention, a molding material paste is filled into the concave portions of an intaglio plate for filling, an intaglio plate for transfer on which a specific groove pattern is formed is partially contacted with the intaglio plate for filling, the molding material is filled into the grooves of the intaglio plate for transfer, then the molding material is transferred from the intaglio plate for transfer to a substrate as a protrusion pattern.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: May 12, 2009
    Assignee: Hitachi Limited
    Inventors: Osamu Toyoda, Kazunori Inoue, Akira Tokai
  • Patent number: 7391389
    Abstract: According to the present invention, drive voltage pulses are applied between a pair of electrodes by driving a first power source having a specific voltage from a state in which the electrodes are maintained at the potential of a reference power source that is different from the potential of the ground power source, and then returning it to the reference power source. As a result, the gas discharge current or capacitance charging and discharging current accompanying the application of the drive voltage pulses is prevented from flowing to the first power source line. The above-mentioned gas discharge current or capacitance charging and discharging current resulting from the application of the drive voltage pulses flows to the first power source or the reference power source electrically separated from the ground power source, and does not flow to the ground power source line, so no noise is generated on the first power source.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: June 24, 2008
    Assignee: Hitachi Limited
    Inventors: Toyoshi Kawada, Masami Aoki
  • Publication number: 20040174948
    Abstract: An image pickup apparatus of a radiological imaging apparatus includes a plurality of radiation detectors arranged in a ring form around a through hole section formed on a casing into which an examinee is inserted. An X-ray source unit having an X-ray source moves in a circumferential direction of the through hole section along a ring-shaped guide rail provided on the casing. Each radiation detector outputs both an X-ray detection signal which is a detection signal of X-rays that have passed through the examinee and a &ggr;-ray detection signal which is a detection signal of &ggr;-rays radiated from the examinee caused by radiopharmaceutical. A computer creates an X-ray computed tomographic image data based on the X-ray detection signal and a PET image data based on the &ggr;-ray detection signal and creates fused tomographic image data using the X-ray computed tomographic image data and the PET image data.
    Type: Application
    Filed: October 27, 2003
    Publication date: September 9, 2004
    Applicant: Hitachi Limited
    Inventors: Shinichi Kojima, Kikuo Umegaki, Takashi Okazaki, Kensuke Amemiya, Hiroshi Kitaguchi, Yuuichirou Ueno
  • Publication number: 20040158791
    Abstract: The present invention discloses an information processing method including the following steps:
    Type: Application
    Filed: October 28, 2003
    Publication date: August 12, 2004
    Applicant: Hitachi Limited
    Inventor: Hideki Sawaguchi
  • Publication number: 20040073731
    Abstract: A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use permission is not given to another channel having a low necessity of a real-time processing operation. The bus arbitrator of the data includes a timer for counting down use permission time with respect to the channel having the high necessity of the real-time processing operation, and a register for the channel having the low necessity of the real-time processing operation. A value larger than a maximum value of the timer is set to the value of the register. In the bus arbitration, the value of the register is compared with that of the timer, and then the bus use permission is given to a channel having the small value.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 15, 2004
    Applicant: Hitachi, Limited
    Inventors: Hiroshi Yamada, Toyokazu Hori, Masaru Hase, Tetsuya Yamato, Norihiko Sugita
  • Publication number: 20040065074
    Abstract: A gas turbine installation which includes a compressor which compresses supplied air and discharges the same, a combustor which combusts the compressed air obtained from the compressor and fuel and produces combustion gas, a turbine which is driven by combustion gas provided from the combustor, a regenerative heat exchanger which heats all or a part of the compressed air being supplied from the compressor to the combustor by making use of the heat of the exhaust gas exhausted from the turbine and a plurality of water spraying devices which are provided at positions from an intake air chamber of the compressor to the outlet of low temperature side gas flow passage in the regenerative heat exchanger and is characterized in that the regenerative heat exchanger is constituted by connecting in series a plurality of heat exchangers having different heat transfer surface configurations.
    Type: Application
    Filed: October 1, 2003
    Publication date: April 8, 2004
    Applicant: Hitachi, Limited
    Inventors: Takanori Shibata, Shigeo Hatamiya, Nobuhiro Seiki, Tomomi Koganezawa, Katsuhiko Sagae
  • Publication number: 20040065812
    Abstract: Disclosed herein is an amusement system that can be used and enjoyed by different persons without using the brain continuously and with little feeling of fatigue and which permits setting a probe at any spot on the head of the subject.
    Type: Application
    Filed: October 1, 2003
    Publication date: April 8, 2004
    Applicant: Hitachi, Limited
    Inventors: Tsuyoshi Yamamoto, Kosuke Ohashi, Hironari Nakata, Atsushi Maki, Hideaki Koizumi, Mitsuru Oonuma
  • Publication number: 20040054865
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Application
    Filed: August 19, 2003
    Publication date: March 18, 2004
    Applicant: Hitachi, Limited
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Publication number: 20040043307
    Abstract: A method of manufacturing an electron device provided with minute structure such as a semiconductor integrated circuit using projection exposure technique and phase shift mask technique, maintaining a high yield is disclosed. In an electron device manufacturing method according to the invention, a desired electron device is manufactured by printing a light shielding film pattern on a photosensitive film provided on the surface of a workpiece by a projection tool using a mask where a phase shifter having predetermined thickness is partially formed on the flat surface of a transparent plate and a light shielding film having a predetermined pattern and made of nonmetal is partially provided with the film covering the end of the shifter and developing the photosensitive film.
    Type: Application
    Filed: September 29, 2003
    Publication date: March 4, 2004
    Applicant: Hitachi, Limited
    Inventors: Toshihiko Tanaka, Norio Hasegawa, Hiroshi Shiraishi, Hidetoshi Satoh
  • Patent number: 6421284
    Abstract: In the conventional column-side block redundancy for DRAM, competition for the replacing regions occurs unless a repair address of a large number of bits is stored in order to replace with a small replacement unit. According to one aspect of the invention, replacement decision is performed in order that a second replacement region can be made smaller than a first replacement and that the second replacement is given priority over the first replacement. Therefore, the first replacement can be controlled by a repair address of a small number of bits, thus making it possible to achieve a semiconductor device having a defect repair circuit with small area and high repair efficiency.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: July 16, 2002
    Assignee: Hitachi, Limited
    Inventor: Takeshi Sakata
  • Publication number: 20020073292
    Abstract: An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
    Type: Application
    Filed: February 5, 2002
    Publication date: June 13, 2002
    Applicant: Hitachi, Limited
    Inventors: Hideki Murayama, Kazuo Horikawa, Hiroshi Yashiro, Masahiko Yamauchi, Yasuhiro Ishii, Daisuke Sasaki
  • Patent number: 6404411
    Abstract: The present specification and drawings disclose a technique to display image on the display panel using subfield. Particularly, it is disclosed that the technique for conducting the reset operation by impressing, to the electrode of cells, a plurality of reset pulses per one subfield in the subfield period for the reset operation and then conducting the address operation for selecting cells for display discharge. Further, it is disclosed that the display technique for causing the cells of display panel to conduct display discharge for image display through the reset operation and address operation. Namely, it is the technique for impressing the auxiliary pulse to the electrode of cells after impression of reset pulse for reset operation to form charges in inverse voltage to the scan pulse during the address operation and then conducting the address operation for selecting the cells for display discharge.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: June 11, 2002
    Assignee: Hitachi, Limited
    Inventors: Takeo Masuda, Takashi Sasaki, Masaji Ishigaki, Hiroshi Ohtaka
  • Publication number: 20020062466
    Abstract: Disclosed herein are a semiconductor integrated circuit and a recording medium wherein the amount of test data inputted from and outputted to the outside to test a plurality of circuit modules and the amount of test result data are reduced and a test time interval is shortened. When each of tested circuits is tested, test control information is externally inputted to a test interface circuit, and test control information is set to each of scan registers of circuit modules to be tested, through a test signal chain. When an instruction for a test operation is given to each of test control circuits through a control terminal, a test circuit allows the tested circuits to be tested based on the test control information on a parallel basis. Test results are read into the test interface circuit from the scan registers through the test signal chain, followed by output to the outside.
    Type: Application
    Filed: January 10, 2002
    Publication date: May 23, 2002
    Applicant: Hitachi, Limited
    Inventor: Koki Noguchi
  • Patent number: 6272225
    Abstract: A key recovery condition encryption apparatus includes a hashing unit, a first concatenating unit, and a condition information encryption unit. The hashing unit calculates a hash value on the basis of a hash function using a key recovery information text serving as information necessary for performing key recovery. The first concatenating unit concatenates the hash value from the hashing unit to the key recovery condition. The condition information encryption unit encrypts a concatenating result from the first concatenating unit by using a first encryption key. Also is disclosed a key recovery condition decryption apparatus for decrypting the encrypted data from the above encryption apparatus.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: August 7, 2001
    Assignees: NEC Corporation, Hitachi Limited, Fujitsu Limited
    Inventors: Hiroshi Miyauchi, Kazue Sako, Masashi Yamazaki, Seiichi Domyo, Hiroyoshi Tsuchiya, Seiko Kanno, Ichirou Morita, Naoya Torii, Hiroyuki Ando, Yasutsugu Kuroda
  • Patent number: 6198863
    Abstract: An optical filter is formed from at least two grating located in a waveguide region of a semiconductor optical device. Each grating has a multiple peak optical passband. The gratings are spaced apart in the waveguide region and form an optical cavity having a comb-filter characteristic. The gratings may be located in the active region of an optical gain element and in a preferred example are superstructure gratings (SSGs). A number of filters may be joined together in series.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: March 6, 2001
    Assignees: British Telecommunications public limited company, Hitachi Limited
    Inventors: Ian F Lealman, Michael J Robertson, Makoto Okai
  • Patent number: 5864414
    Abstract: A wavelength division multiplex communication system comprises a head station (2) and a plurality of terminal stations (1) interconnected by an optical fibre cable (3). The head station (2) transmits continuous wave modulated wavelengths (.lambda..sub.1 -.lambda..sub.k), and a signalling wavelength (.lambda..sub.0) which is used to indicate, in each time slot, which wavelengths in the following time slot are available for transmission. Each terminal station (1) is arranged to receive the signalling wavelength, to determine therefrom whether the next time slot contains any data packets for that terminal station and, if so, to receive the packets. The terminal station (1) is arranged, if it has a data packet to transmit, to determine from the signalling wavelength whether the next time slot already contains data packets for the destination station and, if so, to avoid data collision by not transmitting its own data packet. The terminal station (1) then determines a free wavelength (.lambda..sub.
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: January 26, 1999
    Assignees: British Telecommunications public limited company, Hitachi Limited
    Inventors: Peter E. Barnsley, Alan McGuire, Hideaki Tsushima