Patents Assigned to Hitachi, Ltd.
  • Patent number: 11977876
    Abstract: Provided is an update device capable of appropriately updating the nodes used in business processing. The update device comprises a communication control unit which instructs the load balancer to stop distribution to the first cluster, a transfer unit which instructs the first management node and the second management node to transfer the first execution node from being under management of the first management node to being under management of the second management node, and an update unit which instructs the first management node to update the first management node on grounds that the first execution node being under management of the first management node has been transferred to being under management of the second management node.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventor: Keisuke Takagi
  • Patent number: 11978794
    Abstract: In a SiC power MISFET having a lateral surface of a trench formed in an upper surface of a SiC epitaxial substrate as a channel region, a silicon carbide semiconductor device having low resistance, high performance, and high reliability is realized. As a means therefor, a SiC power MISFET is formed as an island-shaped unit cell on an upper surface of an n-type SiC epitaxial substrate that is provided with a drain region on a bottom surface thereof, the SiC power MISFET including: an n-type current diffusion region that surrounds a p-type body layer contact region and an n-type source region in the indicated order in a plan view; a p-type body layer and an n-type JFET region; a trench that is formed on the body layer so as to span between the source region and the current diffusion region adjacent each other in a first direction and extends in the first direction; and a gate electrode embedded in the trench with a gate insulating film therebetween.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventors: Takeru Suto, Naoki Tega, Naoki Watanabe, Yuki Mori, Digh Hisamoto
  • Patent number: 11977441
    Abstract: This failure tree generation device includes: a causal relationship storage unit that stores information indicating a linkage of the causal relationship of defects of respective component parts constituting subjects to be analyzed in a manner such that the information is associated with the connection relationship of the respective component parts; a system-level failure tree generation unit that generates, for each of the component parts and on the basis of component part constitution information indicating the constitution of component parts to be analyzed and component part connection information indicating the connection relationship of the respective component parts, first element information which is information indicating disturbance having occurred in information transfer between the respective component parts and which indicates the relationship between each of the component parts and a phenomenon having occurred on the component part, and generates, on the basis of the respective items of first elem
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 7, 2024
    Assignee: Hitachi, Ltd.
    Inventor: Yuuki Shimizu
  • Patent number: 11977866
    Abstract: There is provided an application screen display program implementation method for executing application software to display a screen using an information processing apparatus. Each record of a master table for controlling the display of each display element for display elements configuring a screen and transaction data input and output from the display element has a field for holding an index of an array, and association with an index of an array in a source code of an execution program is performed. Therefore, in application development, the required man-hours with respect to the change of the display screen are reduced.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventor: Kiyoko Koizumi
  • Patent number: 11977765
    Abstract: The functions of a mainframe environment are expanded by leveraging the functions of an open environment.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: May 7, 2024
    Assignee: Hitachi, Ltd.
    Inventors: Naoyuki Masuda, Ryusuke Ito, Kenichi Oyamada, Yuri Hiraiwa, Goro Kazama, Yunde Sun, Ryosuke Kodaira
  • Patent number: 11977636
    Abstract: Example implementations described herein provide systems and methods for detecting damage to data by malware and involve generating log information at a storage device based on a write input/output (I/O) provided to the storage device by one or more servers, the log information comprising time information for storing the write I/O to the storage device, logical block information for the write I/O, and a compression ratio associated with storing the write I/O to the storage device; and, for a request by a management server to provide the log information for a specified time range for the storage device, returning, from the storage device, the logical block information and the compression ratio associated with the time information within the specified time range.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventor: Tomohiro Kawaguchi
  • Patent number: 11977433
    Abstract: Aspects of the present disclosure involve an innovative method for detecting error zones from a plurality of volume groups. The method may include creating a plurality of probe groups for error detection; detecting a new error associated with the plurality of probe groups and the plurality of volume groups; retrieving error information associated with the new error, wherein the error information comprises an error source, an error type, and an error time; retrieving an error correlation rule associated with the error information; determining if the error correlation rule is satisfied by the error information and information of other known errors; and identifying a common zone based on the error information and the information of the other known errors as an error zone.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventors: Hiroyuki Osaki, Tomohiro Kawaguchi
  • Patent number: 11977487
    Abstract: In a management node that manages a distributed file and object storage that accessibly manages a file used by an application, the distributed file and object storage is accessible to a file managed by a storage of another site, and a management node includes a processor, and the processor is configured to specify an access circumstance relating to a file by an application, and control caching by the distributed file and object storage of the own site with respect to the file managed by the storage of the other site used by the application, before the application is executed, based on the access circumstance.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventors: Shimpei Nomura, Mitsuo Hayasaka
  • Patent number: 11977362
    Abstract: In the conventional distributed control system, since each control device updates the data area at a timing when a control packet is received, in a case where there is a difference in communication delay between the control devices or in a case where the communication delay includes jitter, it is difficult to match the contents of data in all the control devices in a case of focusing on a certain moment during system operation. Therefore, depending on the start timing of a control application, the control application operates on the basis of different data between the control devices, thus limiting control performance improvement. Accordingly, time slots on the network are allocated according to the result of a calculation unit, and a cyclic memory synchronization update unit synchronizes the timing of reflecting data in the input/output and the cyclic memory and the timing of using data of a cyclic memory.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventors: Tatsuya Maruyama, Yusaku Otsuka, Hidenori Omiya, Toshiki Shimizu, Iori Kobayashi, Kazutaka Onishi, Noritaka Matsumoto
  • Patent number: 11977764
    Abstract: An administrative terminal receives designation of generation target data and of a generation destination storage device and identifies data similar to the target data. The terminal calculates a first predicted time expected for transmitting the target data from a storage device holding the target data to the generation destination storage device, and a second predicted time expected to be required for a second transmission process of transmitting the similar data from an object storage service to the generation destination storage device and of transmitting difference data between the target data and the similar data from the storage device holding the target data to the generation destination storage device. If the second predicted time is shorter than the first predicted time, the administrative terminal performs the second transmission process to transmit the similar data and the difference data to the generation destination storage device to generate the generation target data therein.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventors: Hideyuki Koseki, Akira Deguchi, Masahiro Arai
  • Publication number: 20240143300
    Abstract: A program analyzing apparatus (failure analyzing apparatus) includes an execution path reduction unit that deletes an execution path that is not executed by referring to information related to a branch destination of a conditional branch included in a program, from all execution paths that are all executable execution paths among execution paths that are columns of statements to be sequentially executed in the program.
    Type: Application
    Filed: February 15, 2022
    Publication date: May 2, 2024
    Applicant: HITACHI, LTD.
    Inventors: Hiroto Kaga, Masumi Kawakami, Yasufumi Suzuki
  • Patent number: 11972119
    Abstract: A storage system that can achieve a cryptographic operation circuit that supports multiple types of cryptographic operation formats. The cryptographic operation circuit is provided that encrypts data according to the format determined by the processor based on a request by the host terminal for writing the data into the storage device, and decrypts the encrypted data on the data stored in the storage device according to the format determined by the processor based on a request by the host terminal for reading the data from the storage device.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: April 30, 2024
    Assignee: HITACHI, LTD.
    Inventors: Shumpei Morita, Tomoyuki Kamazuka, Hideaki Monji, Yuusaku Kiyota
  • Patent number: 11971998
    Abstract: A data comparison device holds first and second encrypted data of first and second plaintext, respectively. The first plaintext is divided into a plurality of blocks and the first encrypted data is generated by executing encryption of each of the plurality of blocks and shuffling of the plurality of blocks. The second plaintext is divided into a plurality of blocks and the second encrypted data is generated by executing encryption of each of the plurality of blocks. In at least one of the first encrypted data and the second encrypted data, a plaintext value is embedded as a value indicating a magnitude comparison result, and the data comparison device compares blocks at the same position before shuffling of the first encrypted data and the second encrypted data based on the embedded value and determines a magnitude relationship between the first plaintext and the second plaintext.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: April 30, 2024
    Assignee: HITACHI, LTD.
    Inventors: Masayuki Yoshino, Ken Naganuma, Hisayoshi Sato
  • Patent number: 11972877
    Abstract: A superconducting wire connector includes superconducting wires and a sintered body containing MgB2. The superconducting wires are connected by the sintered body. At least one of the superconducting wires includes a superconducting core having a first outer surface. The sintered body is in contact with the first outer surface. A method of connecting superconducting wires by a sintered body containing MgB2 includes exposing a superconducting core of at least one of the superconducting wires by removing a portion, positioned in the middle in a longitudinal direction of the at least one of the superconducting wires, of a metal sheath disposed around the superconducting core, disposing the at least one of the superconducting wires through a container, filling the container with a raw material of MgB2, and forming the sintered body being in contact with an outer surface of the superconducting core by sintering the raw material filled in the container.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: April 30, 2024
    Assignee: HITACHI, LTD.
    Inventors: Shinji Fujita, Tsuyoshi Wakuda, Yota Ichiki, Motomune Kodama
  • Publication number: 20240137284
    Abstract: An infrastructure design system includes an infrastructure design apparatus configured to generate infrastructure design information including information regarding a server infrastructure in which an application of a solution service is installed and a wireless communication infrastructure that connects the server infrastructure with a place where the solution service is used. The infrastructure design apparatus manages provision cost information regarding each of the wireless communication infrastructure and the server infrastructure, calculates estimated latency at a time of providing the solution service, on the basis of a communication delay between a solution service usage environment and the server infrastructure and a processing delay of the application, selects a combination of the wireless communication infrastructure and the server infrastructure on the basis of the estimated latency and a provision cost, and outputs the combination as infrastructure design information.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 25, 2024
    Applicant: Hitachi, Ltd.
    Inventors: Daisuke MASHIMO, Masayuki TAKASE
  • Patent number: 11967624
    Abstract: Abnormal generation of heat of a power MOSFET is detected to improve the reliability of a semiconductor device. As its means, in a power MOSFET having a drain electrode on the side of a back surface of a semiconductor substrate and a source pad on the side of a main surface of the semiconductor substrate, two gate pads electrically connected to a gate pad connected to a gate electrode of the power MOSFET are formed on the side of the main surface of the semiconductor substrate. Further, there is provided a voltmeter connected in parallel with each of two current paths which connect the two gate pads and a gate driver.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: April 23, 2024
    Assignee: HITACHI, LTD.
    Inventors: Naoki Tega, Digh Hisamoto, Takeru Suto
  • Patent number: 11966716
    Abstract: An information processing apparatus includes an annealing control unit, a spin interaction memory, a random number generation unit, and a spin state update unit and obtains a solution by using an Ising model. The annealing control unit controls an annealing step and a parameter of a temperature and a parameter of a self-action. The spin interaction memory stores the interaction coefficient of a spin. The random number generation unit generates a predetermined random number. The spin state update unit includes a spin buffer that stores values of a plurality of spins, an instantaneous magnetic field calculation unit that calculates instantaneous magnetic fields of the plurality of spins, a probability calculation unit that calculates update probabilities of the plurality of spins, and a spin state determination unit that updates the values of the spins based on the update probabilities and a random number.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 23, 2024
    Assignees: HITACHI, LTD, NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
    Inventors: Normann Mertig, Takashi Takemoto, Shinya Takamaeda, Kasho Yamamoto, Masato Motomura, Akira Sakai, Hiroshi Teramoto
  • Publication number: 20240127481
    Abstract: A sensor position calibration device includes a moving object information acquisition unit that acquires a self-position measured by a reference moving object moving in a movement area; a moving object measurement unit that measures a position of the reference moving object based on observation information of a camera; a calibration unit that calibrates position information of the camera by using the self-position of the moving object and an estimated position calculated based on the measured position and the position information of the camera; a calibration error calculation unit that calculates an error between a second estimated position and the self-position; a reliability map generation unit that, based on the error, generates a reliability map indicating reliability of position measurement in the movement area using the camera; and a moving object control unit that controls movement of the moving object by using the reliability map.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 18, 2024
    Applicant: HITACHI, LTD.
    Inventors: So SASATANI, Tsuyoshi KITAMURA, Takuma OSATO, Haruki MATONO
  • Publication number: 20240126932
    Abstract: A design support device for performing a check of a defect suppresses defects such as rework in product design and manufacturing and appropriately proposing a criterion, which is an item to be checked in accordance with the actual situation. The design support device includes a memory that stores past subject information for a product designed in the past, thereby storing a correspondence table in which criteria indicating check items are associated, an input unit that receives input of new subject information of a product of a new subject to be checked, a priority calculation unit that calculates a priority of the criterion indicating the check item for the product of the new subject corresponding to the input new subject information, using the correspondence table, and an output unit that outputs the calculated criterion on the screen according to the priority.
    Type: Application
    Filed: February 2, 2022
    Publication date: April 18, 2024
    Applicant: Hitachi, Ltd.
    Inventor: Ichiro KATAOKA
  • Patent number: D1024961
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: April 30, 2024
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Suto, Akihiro Namba, Akeshi Takahashi, Makoto Ito