Patents Assigned to HPL Technologies, Inc.
  • Publication number: 20070160281
    Abstract: Detecting spatial failures in a wafer can be performed quickly and accurately by using transformations and cluster signature analysis. For this technique, a system can receive failure coordinates for the wafer, wherein each failure coordinate indicates a spatial failure. A failure array can be generated based on a resolution of those failure coordinates. A first set of objects, e.g. linear and arc objects, can be detected in the failure array using transformations. A second set of objects, e.g. blob and scratch objects, can be detected in the failure array using cluster signature analysis. This technique advantageously reduces the amount of memory required to perform the analysis and increases the processing speed without increasing the error rate of detection.
    Type: Application
    Filed: January 10, 2006
    Publication date: July 12, 2007
    Applicant: HPL Technologies, Inc.
    Inventor: Rafik Marutyan
  • Patent number: 6812751
    Abstract: A low standby current power-on reset circuit is described. A first NMOS transistor's drain is coupled to a first PMOS transistor's drain; source coupled to ground line; and gate coupled to a first capacitor coupled to ground line. The first PMOS transistor's source is coupled to power line; gate coupled to second capacitor coupled to ground line; and drain provides a power-on reset indication. A second PMOS transistor's source is coupled to power line; drain is coupled to drain of second NMOS transistor, gates of first PMOS, second PMOS, and second NMOS transistors, and second capacitor. The second NMOS transistor's source is coupled to gate of first NMOS transistor and first capacitor. A discharge circuit is coupled to power line, ground line, and first and second capacitors for discharging the capacitors when a voltage on power line drops below a level determined by the second PMOS transistor's threshold voltage.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: November 2, 2004
    Assignee: HPL Technologies, Inc.
    Inventors: Agustinus Sutandi, Daran DeShazo, Jason Stevens, Craig Waller
  • Patent number: 6795953
    Abstract: A method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design is described. Described processing includes retrieving conductivity layers information for an integrated circuit design from a GDSII formatted file; defining a dummy polygons layer and a target layer; restoring interconnect polygons from the conductivity layers information into the dummy polygons layer; copying the interconnect polygons from the dummy polygons layer to the target layer, except for dummy interconnect polygons; and performing defect analysis of the integrated circuit design using the target layer.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: September 21, 2004
    Assignee: HPL Technologies, Inc.
    Inventors: Sergei Bakarian, Julie Segal
  • Patent number: 6780656
    Abstract: A method for determining between at least three origins of a coordinate system used for at least three different defect inspection spaces. The method comprises: collecting multiple sets of data spanning defect inspection spaces; filtering the data sets to remove points that introduce noise into correlation calculations; determining whether different data sets show correlation; selecting pairs of data sets showing correlation greater than or equal to a metric; and calculating coordinate offsets of at least three origins based on the selected pairs of data sets.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: August 24, 2004
    Assignee: HPL Technologies, Inc.
    Inventors: David Muradian, John Caywood, Brian Duffy, Julie Segal
  • Patent number: 6741500
    Abstract: An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: May 25, 2004
    Assignee: HPL Technologies, Inc.
    Inventors: Daran DeShazo, Agustinus Sutandi, Jason Stevens
  • Publication number: 20030160627
    Abstract: A method for determining the offset between at least three origins of a coordinate system used for at least three different defect inspection spaces. The method comprises: collecting multiple sets of data spanning defect inspection spaces; filtering the data sets to remove points that introduce noise into correlation calculations; determining whether different data sets show correlation; selecting pairs of data sets showing correlation greater than or equal to a metric; and calculating coordinate offsets of the at least three origins based on the said selected pairs of said data sets.
    Type: Application
    Filed: October 5, 2001
    Publication date: August 28, 2003
    Applicant: HPL Technologies, Inc.
    Inventors: David Muradian, John Caywood, Brian Duffy, Julie Segal