Abstract: A capacitor and a method of manufacturing the same are disclosed. The BST dielectric film is disposed between the lower electrode by coating a sidewall of the upper electrode and then forming the lower electrode in a second contact hole defined by the upper electrode and BST film. As such, degradation in the step coverage characteristic caused by forming a BST dielectric film having a desired composition ratio is avoided.

Abstract: A structure of a lower electrode of a capacitor includes a first lower electrode, second lower electrodes formed at both sides of the first lower electrode and electrically connected to and higher than the first lower electrode, and a Hemispherical Grain-Silicon (HSG-Si) layer formed on a top surface of the first lower electrode and inside walls of the second lower electrodes.

Abstract: The present invention discloses a synchronous memory device capable of processing data at a high speed in a read path of the memory device, by decreasing the timing margin of the external clock signal which is input into the input registers, of the pipeline structure the memory device comprises: a) an address pad receiving an address signal; b) a first input register coupled to the address pad, wherein the first input registers including:, 1) a first switching device coupled to the address pad, wherein the first switching device is controlled by a first control signal; 2) a first latch device for storing the address signal from the first switching device; and 3) a second switching device coupled to the first latch device, wherein the second switching device is controlled by a second control signal, and wherein-the second control signal is 180.degree.