Abstract: The present invention relates to a method of forming a conductive layer and an electroplating device, and in particular, to a method of forming a conductive layer that provides an electrically-conductive layer having both characteristics of increased adhesiveness to an electroplated body and increased uniformity. The electroplating apparatus and method can produce supersonic waves for electroplating. Thus, the electroplating device can include a wave generator. The electroplating device can further include a plating bath filled with an electrolyte solution that can propagate super sonic waves, a power supply, a plated body connected electrically to a first terminal of the power supply, and a plating body connected electrically to a second terminal of the power supply where the plating body provides ions the same as dissolved in the electrolyte solution to maintain a desired concentration of dissolved ions.

Abstract: A capacitor of a semiconductor device is provided which includes a semiconductor substrate and insulating interlayer formed on the semiconductor substrate. The insulating interlayer has a contact hole which exposes a portion of the semiconductor substrate. A plug fills in the contact hole and the plug comes into contact with the semiconductor substrate. A contact layer is formed on the insulating interlayer. The contact layer comes into contact with the plug. First and second barrier layers are formed on the surface and sides of the contact layer, and a lower electrode is formed on the first barrier layer. A dielectric layer formed on the second barrier layer and lower electrode, and an upper electrode is formed on the dielectric layer.

Abstract: A lead frame includes a pair of guide rails separated at a predetermined space; at least one dam bar for connecting the pair of guide rails; a die paddle for mounting a semiconductor chip between the dam bar; a tie bar for supporting the die paddle; a plurality of leads each consisting of a first lead having a predetermined length extended from the dam bar between the dam bar and the die paddle, a second lead connected electrically to the first lead and formed bent in a first direction, and a third lead connected electrically to the second lead and formed bent in a second direction.

Abstract: Provided with a method for forming conductive lines in a semiconductor device including the steps of: (a) forming a first conductive line on a substrate; (b) forming a first insulating layer on the substrate as well as on the first conductive line; (c) etching the first insulating layer on the first conductive line to form a first opening; (d) forming a second insulating layer on the first insulating layer to be in contact with the upper part of the first opening, thereby sealing the first opening; (e) etching the first and second insulating layers corresponding to the first conductive line to form a second opening and at the same time extend the first opening so as to expose the first conductive line; and (f) forming a second conductive line within the first and second openings so as to be connected with the first conductive line, thereby preventing halation caused by irregular reflection during exposure on the second photo resist because the second insulating layer has a less difference in thickness, and su

Abstract: The present invention related to a method of fabricating a semiconductor device which prevents short channel hump due to the moisture in an insulating interlayer. The present invention includes the steps of forming a trench typed field oxide layer defining an active area in a field area of a semiconductor substrate of a first conductive type, forming a gate to the direction of device width wherein a gate oxide layer is inserted between the gate and semiconductor substrate, forming impurity regions in the semiconductor substrate at both sides of the gate by ion implantation with impurities of a second conductive type, forming an insulating interlayer covering the gate on the semiconductor substrate, and removing moisture contained in the insulating interlayer by thermal treatment.

Abstract: The present invention relates to a method of forming a conductive layer and an electroplating device, and in particular, to a method of forming a conductive layer that provides an electrically-conductive layer having both characteristics of increased adhesiveness to an electroplated body and increased uniformity. The electroplating apparatus and method can produce supersonic waves for electroplating. Thus, the electroplating device can include a wave generator. The electroplating device can further include a plating bath filled with an electrolyte solution that can propagate super sonic waves, a power supply, a plated body connected electrically to a first terminal of the power supply, and a plating body connected electrically to a second terminal of the power supply where the plating body provides ions the same as dissolved in the electrolyte solution to maintain a desired concentration of dissolved ions.

Abstract: A capacitor of a semiconductor device is provided which includes a semiconductor substrate and insulating interlayer formed on the semiconductor substrate. The insulating interlayer has a contact hole which exposes a portion of the semiconductor substrate. A plug fills in the contact hole and the plug comes into contact with the semiconductor substrate. A contact layer is formed on the insulating interlayer. The contact layer comes into contact with the plug. First and second barrier layers are formed on the surface and sides of the contact layer, and a lower electrode is formed on the first barrier layer. A dielectric layer formed on the second barrier layer and lower electrode, and an upper electrode is formed on the dielectric layer.

Abstract: The present invention relates to a method of forming a conductive layer and an electroplating device, and in particular, to a method of forming a conductive layer that provides an electrically-conductive layer having both characteristics of increased adhesiveness to an electroplated body and increased uniformity. The electroplating apparatus and method can produce supersonic waves for electroplating. Thus, the electroplating device can include a wave generator. The electroplating device can further include a plating bath filled with an electrolyte solution that can propagate super sonic waves, a power supply, a plated body connected electrically to a first terminal of the power supply, and a plating body connected electrically to a second terminal of the power supply where the plating body provides ions the same as dissolved in the electrolyte solution to maintain a desired concentration of dissolved ions.

Abstract: A capacitor of a semiconductor device is provided which includes a semiconductor substrate, an insulating interlayer formed on the semiconductor substrate, the insulating interlayer having a contact hole which exposes a predetermined portion of the semiconductor substrate, a plug filled in the contact hole, the plug coming into contact with the semiconductor substrate, a contact layer formed on the insulating interlayer, the contact layer coming into contact with the plug, first and second barrier layers formed on the surface and sides of the contact layer, a lower electrode formed on the first barrier layer, a dielectric layer formed on the second barrier layer and lower electrode, and a upper electrode formed on the dielectric layer.

Abstract: A method for forming a metal line in a semiconductor device, in which a resolution is improved for securing a design rule and minimizing a difference of critical dimensions, including the steps of (1) forming a first insulating film and a second insulating film on a substrate, (2) etching the second insulating film to form a second insulating film pattern, (3) depositing a third insulating film on the second insulating film pattern, (4) removing the second insulating film pattern, and (5) forming a metal line layer in a region having the second insulating film pattern removed therefrom.

Abstract: A hardware architecture for mathematical morphology operations such as dilation and erosion of an image signal is provided. A hardware architecture for an image dilation operation includes: a plurality of adders corresponding to the size of the structuring element for adding the image signal and a structuring element symmetrical to the image signal with respect to the origin to output the result; a plurality of stores for temporarily storing the signals output from the plural adders; a comparator for comparing data stored in the plural stores with feedback data to output the maximum data; and an outputting device for outputting the output signal of the comparator as a dilation operation value if the dilation operation with respect to all structuring elements for one image signal is completed and feeding back the output signal of the comparator as input data of the comparator if not.

Abstract: A method for fabricating a metal-oxide-semiconductor field effect transistor (MOSFET) device, includes: a step of dividing a semiconductor substrate into an active region and an isolation region; a step of forming a first insulation layer on the semiconductor substrate; a step of forming a first polycrystal silicon layer on the first insulation layer; a step of forming a first silicide layer on the first polycrystal silicon layer; a step of forming a second insulation layer on the first silicide layer; a step of patterning the second insulation layer; a step of forming a sidewall spacer at the side portions of the second insulation layer pattern; a step of forming a gate by sequentially etching the first silicide layer, the first polycrystal silicon layer and the first insulation layer by using the second insulation layer pattern and the sidewall spacer as a mask; a step for removing the sidewall spacer; a step of forming an oxide film at the side portions of the gate and at the upper portion of the semicondu

Abstract: A sense amplifier control circuit in a semiconductor memory supplies a sense amplifier with two power source voltages with voltage levels different from each other, successively. A first logic gate is supplied with a pair of sense amplifier enabling bar signals which are applied to the first logic gate in order. The first logic gate generates a signal of logic value 0 when at least one of the sense amplifier enabling bar signals has logic value 1. A second logic gate generates a first NMOS sense amplifier enabling bar signal of high level when an output of the first logic gate has logic value 0 and a sense amplifier enabling bar signal has logic value 1. A third logic gate generates a first PMOS sense amplifier enabling bar signal of high level when at least one of an output of the first logic gate and a sense amplifier enabling bar signal has logic value 1. A fourth logic gate generates a signal of logic value 1 when at least one of a plurality of MAT selection bar signals has logic value 0.