Abstract: A closed loop power output calibration system for variable power output wireless devices. The wireless device includes a wireless transceiver having a transmit core coupled to a discrete power amplifier. Power detection circuitry formed in the wireless transceiver provides a detected power level of the power amplifier, and a reference power level, both of which are converted to digital signals using existing I and Q signal analog to digital converters in the receiver core. The digital signals are processed to cancel power distortion and temperature effects to provide a resulting power feedback signal. Corrective control signals are generated in response to the power feedback signal relative to a desired power output level. The gain in the transmit core is then adjusted in response to the corrective control signals such that the power amplifier outputs the target output power level.

Abstract: Peripheral components of a wireless radio system can be controlled by a wireless transceiver. The transceiver stores parallel or serial bit patterns in memory, each bit pattern corresponding to a particular control configuration for one or more peripheral components. A further control device, such as baseband controller, issues an address corresponding to the desired functional operation of the peripheral components to the transceiver. A memory sub-system of the transceiver uses the address to output the appropriate bit pattern. The bit pattern can be provided in parallel to statically control individual control lines, or can be converted into a serial bitstream decodable by a command decoder. The command decoder can then decode the bitstream and locally issue the appropriate control signals for the peripheral components.

Abstract: An adaptive current control circuit for reduced power consumption and minimized gain shift in a variable gain amplifier. An automatic gain control circuit provides gain control voltages in response to a gain control signal. The gain control voltages are used by the variable gain amplifier to set the gain of the output signal for wireless transmit operations. The adaptive current control circuit receives the same gain control voltages for reducing current to the variable gain amplifier during low gain operation, while providing higher currents during high gain operation. The current that is provided is a hybrid mix of proportional to absolute temperature (PTAT) current and complementary to absolute temperature (CTAT) current for minimizing temperature effects on the gain. The ratio of PTAT current and CTAT current is adjustable for specific temperature ranges to further minimize temperature effects on the gain.

Abstract: A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals are processed by a digital processing circuit for providing digital control signals. Some of the digital control signals are converted into an analog control signal to provide fine control of the voltage controlled oscillator, while the remaining digital control signals provide coarse control of the voltage controlled oscillator.

Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated.

Abstract: An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

Abstract: Peripheral components of a wireless radio system can be controlled by a wireless transceiver. The transceiver stores parallel or serial bit patterns in memory, each bit pattern corresponding to a particular control configuration for one or more peripheral components. A further control device, such as baseband controller, issues an address corresponding to the desired functional operation of the peripheral components to the transceiver. A memory sub-system of the transceiver uses the address to output the appropriate bit pattern. The bit pattern can be provided in parallel to statically control individual control lines, or can be converted into a serial bitstream decodable by a command decoder. The command decoder can then decode the bitstream and locally issue the appropriate control signals for the peripheral components.

Abstract: A method and system for dynamically shifting spurious tones away from the desired frequency in a virtual local oscillator receiver, such that any undesired signal residing at such spurious tones are effectively delineated from the desired signal and removed from the RF input signal. The system detects the presence of potential undesired blocker signals in the RF input signal, and initiates an iterative power comparison and mixer signal adjustment loop. As the virtual local oscillator uses two mixer signals, the frequency of one of the mixer signals is adjusted during the loop until the power of the down-converted signal is minimized to a predetermined level. Minimized power in the down-converted signal is indicative of the absence of the blocker signal, since the presence of a relatively high power signal is indicative of a blocker signal overlapping with a desired signal.

Abstract: A CMOS transconductor for cancelling third-order intermodulation is provided. The transconductor includes a transconductance circuit and a tuneable distortion circuit. The transconductance circuit takes an input voltage and generates an output current having a transconductance element and an IM3 element. The distortion circuit takes the same input voltage and generates a current having an IM3 element of equal amplitude and opposite phase to the IM3 element of the transconductance circuit. A controller circuit tunes the distortion circuit to adjust its IM3 element to substantially equal the amplitude of the IM3 of the transconductance circuit. The distortion and transconductance circuits are arranged to sum their output currents thereby effectively cancelling the IM3 elements, leaving the transconductance relatively unmodified.

Abstract: A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals are processed by a digital processing circuit for providing digital control signals. Some of the digital control signals are converted into an analog control signal to provide fine control of the voltage controlled oscillator, while the remaining digital control signals provide coarse control of the voltage controlled oscillator.

Abstract: The invention is directed at a hybrid modulation apparatus which combines a polar modulation circuit and a linear modulation circuit. The hybrid apparatus allows a communications device to function as a polar or a linear modulation circuit with less components as the output of the linear modulation circuit is an input of the polar modulation circuit.

Abstract: A CMOS automatic gain control (AGC) circuit that receives an analog control voltage and generates a temperature compensated gain voltage to linearly control the gain of a variable gain circuit operating in the sub-threshold region. A PTAT circuit having a resistor network coupled to a current mirror circuit operating in the sub-threshold region establishes a current having an proportional relationship to temperature. This current is used as a supply for a voltage to voltage converter circuit which generates an intermediate voltage in response to the analog control voltage. A linearizing circuit operating in the sub-threshold region pre-conditions the intermediate voltage, which is then applied to a variable gain circuit. The variable gain circuit is operated in the sub-threshold region, and the preconditioned intermediate voltage will control the amount of gain to be substantially linear with respect to the analog control voltage, and with a range of about 85 dB.

Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated.