Abstract: A method for increasing a forward biased safe operating area of a device includes forming a gate; and forming a segmented source close to the gate, wherein the segmented source includes first segments associated with a first threshold voltage and second segments associated with a second threshold voltage different from the first threshold voltage, wherein at least one device characteristic associated with the first segments is different from the same device characteristic associated with the second segments.

Abstract: A packaged power device includes a ceramic package body having a top drain pad having a first area, a top source pad having a second area smaller than the first area, and a top gate pad having a third area smaller than the second area; a power device having a bottom surface affixed to a top drain pad, a die source pad coupled to the top source pad, and a die gate pad coupled to the top gate pad; and a ceramic lid affixed to the ceramic package body to form the packaged power device.

Abstract: A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.

Abstract: A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

Abstract: A semiconductor device includes a semiconductor body having first and second opposing surfaces, an active area including active transistor cells, and an edge termination region laterally surrounding the active area. Each active transistor cell includes a mesa and a columnar trench having a field plate. The edge termination region includes inactive cells each including a columnar termination trench having a field plate, and a termination mesa including a drift region of a first conductivity type. The edge termination region includes a transition region laterally surrounding the active region and an outer termination region laterally surrounding the transition region. In the transition region, the termination mesa includes a body region of a second conductivity type arranged on the drift region. In the outer termination region, the drift region extends to the first surface. A buried doped region of the edge termination region is positioned in the transition and outer termination regions.

Abstract: A method for increasing a forward biased safe operating area of a device includes forming a gate; and forming a segmented source close to the gate, wherein the segmented source includes first segments associated with a first threshold voltage and second segments associated with a second threshold voltage different from the first threshold voltage, wherein at least one device characteristic associated with the first segments is different from the same device characteristic associated with the second segments.

Abstract: A method includes providing a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, forming a switching device in an active region of the semiconductor substrate, the switching device having electrically conductive gate and field electrodes, forming an intermetal dielectric layer on the main surface over the active region and an inactive region that is laterally spaced apart from the active region, forming a source pad in the first metallization layer over the active region, forming a resistor trench in the inactive region, the resistor trench having a resistance section that is disposed below the main surface, and forming an electrical connection between the source pad and the field electrode that comprises the resistor. The resistor forms an exclusive current path between the source pad and the field electrode.

Abstract: Voltage converter inlay modules are provided for embedding within a package substrate, and are configured to supply power to a processor, or similar digital circuit, which is mounted to the package substrate. The package substrate is typically mounted to a circuit board, or similar. The circuit board provides high-voltage, low-current power to the voltage converter module which, in turn, provides low-voltage high-current power to the processor. The voltage converter inlay provides largely vertical current conduction from the circuit board to the processor, thereby reducing conduction losses incurred by lateral current conduction. The location of the voltage converter inlay between the circuit board and the microprocessor minimizes radiation of electromagnetic interference. The number of terminals allocated for providing power to the package substrate may be minimized due to the voltage converter inlay inputting fairly low levels of current.

Abstract: In an embodiment, a semiconductor package includes at least one die pad, a plurality of outer contacts, a first semiconductor device and a second semiconductor device. The second semiconductor device includes a first transistor device having a source electrode, a gate electrode, a drain electrode, a front surface, and a rear surface. A front metallization is positioned on the front surface and a rear metallization on the rear surface of the second semiconductor device. The front metallization includes a first power contact pad coupled to the source electrode and mounted on the at least one die pad. The rear metallization includes a second power contact pad electrically coupled to the drain electrode, and an auxiliary lateral redistribution structure electrically insulated from the second power contact pad and the drain electrode. The first semiconductor device is electrically coupled to the auxiliary lateral redistribution structure.

Abstract: A method of manufacturing a semiconductor device is described. The method includes depositing a photoresist layer over a semiconductor substrate. The photoresist layer is patterned to form an opening in the photoresist layer. A copper pillar is formed in the opening. A diffusion barrier layer is formed over the copper pillar and over a photoresist portion of the photoresist layer directly adjoining the opening. A solder structure is deposited over the diffusion barrier layer.

Abstract: A packaged power device includes a ceramic package body having a top drain pad having a first area, a top source pad having a second area smaller than the first area, and a top gate pad having a third area smaller than the second area; a power device having a bottom surface affixed to a top drain pad, a die source pad coupled to the top source pad, and a die gate pad coupled to the top gate pad; and a ceramic lid affixed to the ceramic package body to form the packaged power device.

Abstract: Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.

Abstract: A power supply includes a reference voltage generator circuit, a ramp generator circuit, and control circuitry. During operation, the reference voltage generator circuit compares a magnitude of a received output voltage feedback signal to a received reference voltage. Based on the comparison, the reference voltage generator circuit produces a varying reference voltage and outputs it to the ramp generator circuit. As its name suggests, a magnitude of the varying reference voltage varies over time. The ramp generator circuit produces a ramp voltage signal, a magnitude of which is offset by the varying reference voltage. To maintain an output voltage of the power supply within regulation, the control circuitry receives the varying reference voltage and controls activation of a power converter circuit to power a load based on a comparison of the ramp voltage signal and the output voltage feedback signal of the power supply.

Abstract: According to an embodiment of a semiconductor device, the device includes a semiconductor substrate having a transistor region and a diode region. The transistor region includes a plurality of IGBT cells, and a charge carrier compensation region configured to expel or admit drift zone minority charge carriers based on an on-state or an off-state of the IGBT cells. The diode region includes a plurality of diode cells. An isolation structure is provided between the transistor region and the diode region. The isolation structure includes a first trench extending lengthwise along at least part of a periphery of the diode region and a second trench interposed between the first trench and the transistor region. The charge carrier compensation region extends to the second trench of the isolation structure but not the first trench such that the charge carrier compensation region is electrically isolated from an anode potential of the diode region.

Abstract: A method of manufacturing a semiconductor device includes: forming one or more device epitaxial layers over a main surface of a doped Si base substrate; forming a diffusion barrier structure including alternating layers of Si and oxygen-doped Si in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers; and forming a gate above the diffusion barrier structure.

Abstract: A power device includes a gate, and a segmented source adjacent to the gate, wherein the segmented source includes segments having a first threshold voltage and includes segments having a second threshold voltage different from the first threshold voltage.

Abstract: A device includes a cell, wherein each cell includes a body having a main top surface and a main bottom surface, a gate on the main surface on the device having a first length, a gate isolation layer over the gate having a second length at least twice as long as the first length, a source contact in the device body adjacent to the gate, a source metal layer over the gate isolation layer, and a drain on the main bottom surface of the cell.

Abstract: A power module includes: an embedding structure comprising an electrically insulating body, first terminals at a first side of the electrically insulating body, and second terminals at a second side of the electrically insulating body opposite the first side; a first semiconductor chip embedded in the electrically insulating body and comprising a vertical low-side power transistor; and a second semiconductor chip contacting the first set of terminals at the first side of the electrically insulating body and comprising a lateral high-side power transistor. The lateral high-side power transistor is electrically connected to the vertical low-side power transistor through one or more first electrically conductive paths embedded in the electrically insulating body to form a switch node of a half bridge circuit. The switch node is electrically connected to a corresponding one of the second terminals through one or more second electrically conductive paths embedded in the electrically insulating body.

Abstract: A Schottky diode includes a cathode terminal in a high voltage region of a semiconductor die, an anode terminal in a low voltage region of the semiconductor die, where the anode terminal and the cathode terminal are separated by a junction isolation termination situated between the high voltage region and the low voltage region. The Schottky diode includes a junction barrier Schottky diode or a trench metal-oxide-semiconductor (MOS) Schottky diode. The junction isolation termination includes pzener rings. The semiconductor die includes a substrate of a first conductivity type, an epitaxial layer of a second conductivity type situated on the substrate, a well region of the second conductivity type situated in the epitaxial layer in the high voltage region, and coupled to the cathode terminal, a Schottky barrier situated on the epitaxial layer in the low voltage region, and coupled to the anode terminal.

Abstract: A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (IDL) over the gate conductive filler. The method further comprises forming a contact implant at a bottom of the contact trench, and forming a barrier layer in the contact trench.