Abstract: A method in which a resist layer is applied to a base layer is disclosed. The resist layer includes an adhesive material, and the adhesive force of the adhesive material decreases or increases during an irradiation process. Residues of the resist layer may be stripped using the disclosed method.

Abstract: A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.

Abstract: In a method and device measuring a delay time of a section of a digital circuit, an output signal of the section is saved in different memory locations with a clock and earlier by a time interval with respect to the clock, different durations being assigned to the time interval. The delay time is determined as a function of the greatest of the different durations during which a test proceeds in a positive manner. The test proceeds in a positive manner if the value saved with the clock corresponds with the value saved so as to be earlier by the corresponding time interval.

Abstract: In an interface circuit for connection to an output of a frequency converter, at least two current paths are coupled to one another in parallel. Each current path includes at least one cascode stage for signal processing. The circuit compensates for DC voltage offsets of the frequency converter, and has a gain ratio that can be changed over for signals with a large dynamic range.

Abstract: Interconnected master and slave transceivers provide data communication between host computers. Each transceiver receives and encodes elements of a first data sequence from its local host computer at a first rate and employs a finite impulse response (FIR) filter to interpolate elements of the encoded first data sequence to produce elements of a second data sequence at a higher second rate controlled by a local clock signal. The second data sequence controls the amplitude of an analog signal sent to the other transceiver. Each transceiver also processes the analog signal arriving from the other transceiver to produce elements of a third data sequence at that second rate and employs a second FIR filter for Interpolating the third data sequence to produce elements of a fourth data sequence at the slower first rate. Fourth data sequence elements are then decoded to produce elements of a fifth sequence forwarded to the local host computer at the first rate.

Abstract: A thread selection unit for a block multi-threaded processor includes a priority thread selector and an execution thread selector. The priority thread selector uses a maxtime register for each active thread to limit the time an active thread can be the priority thread. The execution thread selector is configured to select the priority thread as the execution thread when the priority thread is unblocked. However, if the priority thread is blocked, the execution thread selector selects a non-priority thread as the execution thread.

Abstract: An embedded processor architecture includes a processing core with configurable memory system. Memory components can be inserted, omitted and resized in different configuration of the memory system without causing irregular features that may cause wasted silicon area. Furthermore, all the various configurations of the memory system are designed to interface with the processing core so that the processing core can be reused without change.

Abstract: A microprocessor system includes a multi-bank memory having a first memory bank and a second memory bank, a muxing circuit, a CPU and a DMA controller. The muxing circuit allows the CPU to access one of the memory bank while allowing the DMA controller access to the other memory bank at the same time. Thus, the microprocessor system needs to process multiple data sets, the CPU can be processing a first data set in the first memory bank while the DMA controller is writing a second data set in the second memory bank. When the CPU is finished processing the first data set and the DMA controller is finished writing the second data set, the muxing circuit is reconfigured so that the CPU can process the second data set in the second memory bank and the DMA controller can write a third data set in the first memory bank.

Abstract: A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.

Abstract: A microprocessor system includes an address generator, an address selector, and memory system having multiple memory towers, which can be independently addressed. The address generator simultaneously generates a first memory address and a second memory address that is 1 row greater than the first memory address. The address selector determines whether the row portion of the first memory address or the second memory address is used for each memory tower. Because each tower can be addressed independently, a single memory access can be used to access data spanning multiple rows of the memory system.

Abstract: A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.

Abstract: A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.

Abstract: A system and method for finding a defective tool in a semiconductor fabrication facility is disclosed. When the tools process the wafers, data representing the time period during which each wafer passes through each tool is sent to a database. The wafers are tested for defects, and lots having wafers with common failure signatures are determined. A lot list for each tool is generated, a positive weight value is assigned to each bad lot, and a negative weight value is assigned to each good lot. A cumulative value is calculated for each tool by sequentially adding the weight values of each lot in the lot list and keeping the cumulative value above or equal to zero. The tool with the largest maximum cumulative value is the tool that is most likely to be defective.

Abstract: A wafer supporting plate suitable for supporting a wafer during a semiconductor-forming process. In particular, the present invention relates to a wafer supporting plate capable of sensing the positioning condition of the wafer on the supporting plate during a heat treatment or other semiconductor-forming processes for detecting whether the wafer is being positioned normally on the supporting plate. The wafer supporting plate comprises a supporting plate body, at least three supporting props disposed on the supporting plate body for receiving and supporting a wafer, at least three sensing devices each disposed besides the supporting props and within the range encircled by the supporting props on the supporting plate body respectively.

Abstract: A method of preparing for structural analysis a deep trench-type capacitor formed in a die employs a combination of mechanical and chemical action to expose the trench-type capacitors. The method of preparing the die includes the steps of (a) mechanically treating the die back side so as to remove a first portion of the substrate and leave intact a second portion of the substrate; (b) mounting the mechanically treated die by affixing the die by its top side to a mount; and (c) chemically treating the mounted die so as to remove the substrate second portion and provide a chemically treated die. By exposing the deep trench capacitors, the method facilitates the inspection of the device for the detection of possible structural defects such as metal shorts, capacitor holes, and particle failures. The method further overcomes the deficiencies associated with conventional methods of substrate removal, and facilitates inspection by a variety of methods.

Abstract: A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad silicon nitride (Si3N4) uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.

Abstract: A device for chemical-mechanical polishing. The device can be applied to a chemical polishing table spinning in a fixed direction and a polishing pad above of it. A chemical-mechanical polishing device according to the present invention is at least comprised of a main body of conditioner with a plurality of mounting pads, wherein each mounting pad is mounted with the diamond granules and located on the lower surface of conditioner, distributed on the rim of main body of each mounting pad. It can contact with polishing pads when cleaning the polishing pads and a number of cavities are across the upper and lower surfaces of each main body of conditioner and distributed between each mounting pads as well. When using the conditioners to clean out the polishing pads, the de-ionized water will flow through the cavities to wash off the acid or basic slurry to eliminate the destruction made by the solders around the diamond granules to extend the durability of the conditioner.