Abstract: In some implementations, a sensor may determine a delay latency value associated with an amount of time from completion of a set of sensor tasks to an actual time of reception of a trigger to selectively transmit or sample sensor data. The sensor may calculate a deviation of the delay latency value from a target delay latency. The sensor may transmit a data frame including an indication associated with the deviation of the delay latency value from the target delay latency.

Abstract: A time-of-flight (ToF) image sensor system includes a pixel array, where each pixel of the pixel array is configured to receive a reflected modulated light signal and to demodulate the reflected modulated light signal to generate an electrical signal; a plurality of analog-to-digital converters (ADCs), where each ADC is coupled to at least one assigned pixel of the pixel array and is configured to convert a corresponding electrical signal generated by the at least one assigned pixel into an actual pixel value; and a binning circuit coupled to the plurality of ADCs and configured to generate at least one interpolated pixel, where the binning circuit is configured to generate each of the at least one interpolated pixel based on actual pixel values corresponding to a different pair of adjacent pixels of the pixel array, each of the at least one interpolated pixel having a virtual pixel value.

Abstract: An electronic inhalation apparatus including a body having a chip module accommodating region which is at least partially surrounded by a folding structure. When a chip module is accommodated in the chip module accommodating region, the folding structure is bent around the chip module in order to fasten the chip module.

Abstract: A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.

Abstract: A method of manufacturing a semiconductor device includes: providing a silicon carbide substrate that includes device regions and a grid-shaped kerf region laterally separating the device regions; forming a mold structure on a backside surface of the grid-shaped kerf region; forming backside metal structures on a backside surface of the device regions; and separating the device regions, wherein parts of the mold structure form frame structures laterally surrounding the backside metal structures.

Abstract: Some examples relate to a method. In the method, a write transaction is routed from a master device to a slave device through a communication path. The communication path includes a first bridge and a second bridge downstream of the first bridge. The first bridge and the second bridge are coupled to one another via an interface structure. The first bridge sets a write busy signal on the communication path when the write transaction is processed by the first bridge; and in response to the first bridge setting the write busy signal, the second bridge holds the write busy signal until the write transaction has been received by the slave device. Upon the slave device receiving the write transaction, the second bridge resets the write busy signal to propagate the reset write busy signal back to the master device through the first bridge.

Abstract: An RF switch device includes transistors coupled in series forming an RF conductive current path; a first resistive bias network forming a DC conductive bias path between gate nodes of the plurality of transistors; and a first ESD bias component coupled between the RF conductive current path and the first resistive bias network, wherein the first ESD bias component provides a DC conductive path between the RF conductive current path of the RF switch device and the first resistive bias network during an ESD event.

Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

Abstract: In some implementations, an angle sensor may determine an angular position of an object based on first sensor values received from a first set of sensing elements. The first sensor values include a first x-component of a magnetic field and a first y-component of the magnetic field. The angle sensor may determine the angular position of the object based on second sensor values received from a second set of sensing elements. The second sensor values include a second x-component of the magnetic field and a second y-component of the magnetic field. The angle sensor may perform a set of safety checks, including performing an x-component check based on the first x-component and the second x-component and performing a y-component check based on the first y-component and the second y-component. The angle sensor may provide an indication of a result of the set of safety checks.

Abstract: A power semiconductor module includes: an electrically insulative frame having opposite first and second mounting sides, and a border that defines a periphery of the electrically insulative frame; a first substrate seated in the electrically insulative frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a plurality of busbars attached to the first substrate and extending through the border of the electrically insulative frame; a plurality of fixing positions at the first mounting side of the electrically insulative frame; and a plurality of electrically insulative protrusions jutting out from the second mounting side of the electrically insulative frame, wherein the protrusions are vertically aligned with the fixing positions.

Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.

Abstract: A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.

Abstract: A radar system includes a signal generator configured to generate an RF signal; a modulator configured to generate an RF test signal by modulating the RF signal with a test signal; a transmitting channel configured to generate an RF output signal based on the RF signal; and a receiving channel configured to receive an antenna signal and the RF test signal and down-convert a superposition of the two signals to baseband by means of a mixer in order to obtain a baseband signal. The radar system further includes an analog-to-digital converter configured to generate a digital radar signal based on the baseband signal, and a computing unit configured to filter the digital radar signal by means of a digital filter, wherein the filter characteristic of the digital filter has a pass band, a transition band, and a stop band. The test signal has a frequency in the transition band.

Abstract: A sensor arrangement comprises a communication device and a sensor element. The sensor element is configured to record a property and provide a sensor signal that represents the property. The sensor arrangement comprises a security element configured to provide a secret. The sensor arrangement is configured to link the sensor signal to the secret to obtain a linked sensor signal, transmit the linked sensor signal to a communication partner using the communication device, obtain a test signal from the communication partner using the communication device, and perform a check to determine whether the test signal comprises the secret.

Abstract: A method for a slave bus and a master bus includes receiving a first frame via a first data channel, wherein the first frame includes at least first header data, first payload data and first checksum. The method further includes implementing a function depending on the header data contained in the received first frame, and generating a second frame including second header data, second payload data, which are determined by the implemented function, and a second checksum. The second checksum is ascertained at least on the basis of the second payload data and the first header data contained in the received first frame. The method also includes transmitting the second frame via a second data channel simultaneously with receiving the first frame via the first data channel.

Abstract: An electronic chip is disclosed. In one example, the electronic chip comprises a substrate comprising a central portion and an edge portion around at least part of the central portion. An active region is arranged in the central portion. A crack guiding structure combined with a crack stop structure is provided, both being arranged in the edge portion.

Abstract: A gas sensing device includes one or more chemo-resistive gas sensors; one or more heat sources, wherein the gas sensors are heated according to one or more first temperature profiles during the recovery phases and according to one or more second temperature profiles during the sense phases; a preprocessing processor for generating preprocessed signal samples; a feature extraction processor for extracting one or more feature values from the received preprocessed signal samples; and a gas concentration processor for creating a sensing result, wherein the gas concentration processor includes a classification processor for outputting a class decision value, wherein the classification processor is configured for outputting a confidence value, wherein the classification processor includes a first trained model based algorithm processor, wherein the gas concentration processor comprises a quantification processor for creating an estimation value, and wherein the quantification processor comprises a second trained m

Abstract: A magnetic field sensor includes a sensor and a processing circuit. The sensor is designed to generate on the basis of a varying magnetic field an oscillation signal that fluctuates around a mean value. The processing circuit is designed to generate an output signal on the basis of the oscillation signal. The processing circuit is designed, in a high-resolution mode different than a low-resolution mode, in each case to generate a mean value crossing pulse in the output signal when the oscillation signal attains the mean value, and to generate in each case a limit value crossing pulse in the output signal when the oscillation signal attains at least one limit value different than the mean value. A pulse width of at least either the mean value crossing pulse or the limit value crossing pulse is set to indicate that the magnetic field sensor is operating in the high-resolution mode.

Abstract: A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between first and second terminals, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. One first diode is electrically coupled in parallel to each switching device of the first type. One second diode is electrically coupled in parallel to each switching device of the second type. The switching devices are arranged in a power semiconductor module having first and second longitudinal sides and first and second narrow sides. The first type switching devices and first diodes are arranged alternatingly in one row along the first longitudinal side. The second type switching devices and second diodes are arranged alternatingly in another row along the second longitudinal side. An axis of symmetry that extends perpendicular to the first and second narrow sides.

Abstract: A semiconductor assembly includes a semiconductor package that includes first and second transistor dies embedded within a package body, the first and second transistor dies being arranged laterally side by side within the package body such that a first load terminal of the first transistor die faces an upper surface of the package body and such that a second load terminal of the second transistor die faces the upper surface of the package body, and a discrete capacitor mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly over and electrically connected to the first load terminal of the first semiconductor die and such that a second terminal of the discrete capacitor is directly over and electrically connected with the second load terminal of the second semiconductor die.