Patents Assigned to Infineon Technologies AG
  • Patent number: 11994613
    Abstract: A radar device is provided comprising a first processing unit, a radar circuitry, at least one security circuitry, at least one secure memory, and a secure interface arranged for communicating with a second processing unit that is external to the radar device, wherein the first processing unit is arranged to configure and/or run the radar device based on parameters obtained via the secure interface from the second processing unit.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: May 28, 2024
    Assignee: Infineon Technologies AG
    Inventors: Andre Roger, Romain Ygnace
  • Patent number: 11995015
    Abstract: Systems, methods, circuits, and devices for data protection are provided. In one example, a data processing device incudes a Physical Unclonable Function (PUF) source that is configured to generate PUF values, a bus, a plurality of bus access components that are configured to access the bus, and a masking information generation circuit. The masking information generation circuit is configured to generate masking information for at least one pair of bus access components using at least one PUF value and to transmit said information to the bus access components. The pair is configured in such a way that one bus access component masks the data according to the masking information generated for the pair before the data is sent over the bus and the other bus access component de-masks the data received over the bus according to the masking information generated for the pair.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: May 28, 2024
    Assignee: Infineon Technologies AG
    Inventors: Ning Chen, Jens Rosenbusch
  • Patent number: 11994891
    Abstract: A voltage regulating circuit including a conversion circuit configured to convert a voltage pulse sequence into a filtered analog voltage, wherein the voltage pulse sequence represents a predefined operating limiting voltage, and a regulator configured to receive the filtered analog voltage as regulation variable and to regulate an output voltage of the voltage regulating circuit to a predefined desired voltage.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: May 28, 2024
    Assignee: Infineon Technologies AG
    Inventors: Christoph Mayerl, Albert Missoni, Christoph Saas
  • Patent number: 11994387
    Abstract: An inductive sensor may include a first angle measurement path associated with determining an angular position based on a first set of input signals. The inductive sensor may include a second angle measurement path associated with determining an angular position based on a second set of input signals. The inductive sensor may include an amplitude regulation path associated with regulating amplitudes of a set of output signals. The inductive sensor may include a safety path associated with performing one or more safety checks. Each safety check of the one or more safety checks may be associated with at least one of the first angle measurement path, the second angle measurement path, or the amplitude regulation path.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: May 28, 2024
    Assignee: Infineon Technologies AG
    Inventors: Friedrich Rasbornig, Dirk Hammerschmidt, Tobias Werth
  • Patent number: 11994890
    Abstract: The present disclosure describes a device for determining information regarding a connection of a circuit component that is connected to an output of a regulator in order to reduce fluctuations of an output signal at the output of the regulator. The device includes a processing unit that is configured to generate a statistical value that is a measure of fluctuations of the measurement signals, and thus of the output signal at the output of the regulator, based on a plurality of measurement signals, each of which has information regarding the output signal of the regulator and is recorded while a load component generates an electrical load at the output of the regulator. The processing unit is configured to compare the statistical value with a limit value and to determine the information regarding the connection of the circuit component based on the result of the comparison.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: May 28, 2024
    Assignee: Infineon Technologies AG
    Inventors: Ronny Andreas Schomacker, Markus Huemer, Christoph Schertz
  • Patent number: 11991062
    Abstract: In some implementations, a sensor may determine a delay latency value associated with an amount of time from completion of a set of sensor tasks to an actual time of reception of a trigger to selectively transmit or sample sensor data. The sensor may calculate a deviation of the delay latency value from a target delay latency. The sensor may transmit a data frame including an indication associated with the deviation of the delay latency value from the target delay latency.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: May 21, 2024
    Assignee: Infineon Technologies AG
    Inventors: Christof Michenthaler, Thomas Hafner, Benjamin Kollmitzer, Alexander Plautz, Andrea Possemato, Constantin Stroi
  • Patent number: 11986021
    Abstract: An electronic inhalation apparatus including a body having a chip module accommodating region which is at least partially surrounded by a folding structure. When a chip module is accommodated in the chip module accommodating region, the folding structure is bent around the chip module in order to fasten the chip module.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: May 21, 2024
    Assignee: Infineon Technologies AG
    Inventors: Jens Pohl, Thea Goetz, Frank Pueschner, Thomas Spoettl
  • Patent number: 11991341
    Abstract: A time-of-flight (ToF) image sensor system includes a pixel array, where each pixel of the pixel array is configured to receive a reflected modulated light signal and to demodulate the reflected modulated light signal to generate an electrical signal; a plurality of analog-to-digital converters (ADCs), where each ADC is coupled to at least one assigned pixel of the pixel array and is configured to convert a corresponding electrical signal generated by the at least one assigned pixel into an actual pixel value; and a binning circuit coupled to the plurality of ADCs and configured to generate at least one interpolated pixel, where the binning circuit is configured to generate each of the at least one interpolated pixel based on actual pixel values corresponding to a different pair of adjacent pixels of the pixel array, each of the at least one interpolated pixel having a virtual pixel value.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: May 21, 2024
    Assignee: Infineon Technologies AG
    Inventor: Krum Beshinski
  • Patent number: 11989145
    Abstract: Some examples relate to a method. In the method, a write transaction is routed from a master device to a slave device through a communication path. The communication path includes a first bridge and a second bridge downstream of the first bridge. The first bridge and the second bridge are coupled to one another via an interface structure. The first bridge sets a write busy signal on the communication path when the write transaction is processed by the first bridge; and in response to the first bridge setting the write busy signal, the second bridge holds the write busy signal until the write transaction has been received by the slave device. Upon the slave device receiving the write transaction, the second bridge resets the write busy signal to propagate the reset write busy signal back to the master device through the first bridge.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: May 21, 2024
    Assignee: Infineon Technologies AG
    Inventors: Frank Hellwig, Glenn Ashley Farrall, Darren Galpin, Sandeep Vangipuram
  • Patent number: 11990520
    Abstract: A method of manufacturing a semiconductor device includes: providing a silicon carbide substrate that includes device regions and a grid-shaped kerf region laterally separating the device regions; forming a mold structure on a backside surface of the grid-shaped kerf region; forming backside metal structures on a backside surface of the device regions; and separating the device regions, wherein parts of the mold structure form frame structures laterally surrounding the backside metal structures.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: May 21, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Andre Brockmeier, Guenter Denifl, Ronny Kern, Michael Knabl, Matteo Piccin, Francisco Javier Santos Rodriguez
  • Patent number: 11990468
    Abstract: An RF switch device includes transistors coupled in series forming an RF conductive current path; a first resistive bias network forming a DC conductive bias path between gate nodes of the plurality of transistors; and a first ESD bias component coupled between the RF conductive current path and the first resistive bias network, wherein the first ESD bias component provides a DC conductive path between the RF conductive current path of the RF switch device and the first resistive bias network during an ESD event.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: May 21, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Valentyn Solomko, Semen Syroiezhin, Mirko Scholz
  • Patent number: 11990405
    Abstract: A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: May 21, 2024
    Assignee: Infineon Technologies AG
    Inventor: Michael Stadler
  • Patent number: 11984392
    Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 14, 2024
    Assignee: Infineon Technologies AG
    Inventors: Chee Yang Ng, Stefan Woetzel, Edward Fuergut, Thai Kee Gan, Chee Hong Lee, Jayaganasan Narayanasamy, Ralf Otremba
  • Patent number: 11982526
    Abstract: In some implementations, an angle sensor may determine an angular position of an object based on first sensor values received from a first set of sensing elements. The first sensor values include a first x-component of a magnetic field and a first y-component of the magnetic field. The angle sensor may determine the angular position of the object based on second sensor values received from a second set of sensing elements. The second sensor values include a second x-component of the magnetic field and a second y-component of the magnetic field. The angle sensor may perform a set of safety checks, including performing an x-component check based on the first x-component and the second x-component and performing a y-component check based on the first y-component and the second y-component. The angle sensor may provide an indication of a result of the set of safety checks.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 14, 2024
    Assignee: Infineon Technologies AG
    Inventor: Dirk Hammerschmidt
  • Patent number: 11978684
    Abstract: A power semiconductor module includes: an electrically insulative frame having opposite first and second mounting sides, and a border that defines a periphery of the electrically insulative frame; a first substrate seated in the electrically insulative frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a plurality of busbars attached to the first substrate and extending through the border of the electrically insulative frame; a plurality of fixing positions at the first mounting side of the electrically insulative frame; and a plurality of electrically insulative protrusions jutting out from the second mounting side of the electrically insulative frame, wherein the protrusions are vertically aligned with the fixing positions.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: May 7, 2024
    Assignee: Infineon Technologies AG
    Inventors: Tomas Manuel Reiter, Peter Bayer, Christoph Koch
  • Patent number: 11978693
    Abstract: A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: May 7, 2024
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Ulrich Froehler, Ralf Otremba, Andreas Riegler
  • Patent number: 11978700
    Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: May 7, 2024
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Peter Kanschat
  • Patent number: 11977180
    Abstract: A radar system includes a signal generator configured to generate an RF signal; a modulator configured to generate an RF test signal by modulating the RF signal with a test signal; a transmitting channel configured to generate an RF output signal based on the RF signal; and a receiving channel configured to receive an antenna signal and the RF test signal and down-convert a superposition of the two signals to baseband by means of a mixer in order to obtain a baseband signal. The radar system further includes an analog-to-digital converter configured to generate a digital radar signal based on the baseband signal, and a computing unit configured to filter the digital radar signal by means of a digital filter, wherein the filter characteristic of the digital filter has a pass band, a transition band, and a stop band. The test signal has a frequency in the transition band.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: May 7, 2024
    Assignee: Infineon Technologies AG
    Inventors: Grigory Itkin, Stefan Herzinger
  • Patent number: 11977508
    Abstract: A method for a slave bus and a master bus includes receiving a first frame via a first data channel, wherein the first frame includes at least first header data, first payload data and first checksum. The method further includes implementing a function depending on the header data contained in the received first frame, and generating a second frame including second header data, second payload data, which are determined by the implemented function, and a second checksum. The second checksum is ascertained at least on the basis of the second payload data and the first header data contained in the received first frame. The method also includes transmitting the second frame via a second data channel simultaneously with receiving the first frame via the first data channel.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: May 7, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Jens Barrenscheen, Ansgar Pottbaecker
  • Patent number: 11977646
    Abstract: A sensor arrangement comprises a communication device and a sensor element. The sensor element is configured to record a property and provide a sensor signal that represents the property. The sensor arrangement comprises a security element configured to provide a secret. The sensor arrangement is configured to link the sensor signal to the secret to obtain a linked sensor signal, transmit the linked sensor signal to a communication partner using the communication device, obtain a test signal from the communication partner using the communication device, and perform a check to determine whether the test signal comprises the secret.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: May 7, 2024
    Assignee: Infineon Technologies AG
    Inventors: Thomas Leutgeb, Markus Dielacher, Norbert Druml, Armin Krieg