Patents Assigned to Infinera Corp.
  • Patent number: 10505655
    Abstract: Methodologies and systems that pass signals between control planes of nodes within a FlexE Network also conforming to the Generalized Multiprotocol Label Switching (GMPLS) protocol are described. The signals passed between the control planes conform to the GMPLS protocol and comprise a FlexE Ethernet Group Number and identify at least one Ethernet PHY conforming to the requirements of IEEE 802.3-2015. The Flexible Ethernet Group Number and the at least one Ethernet PHY are stored in non-transitory memory accessible by a node within the FlexE Network. Then, the node configures a FlexE Group based upon the Flexible Ethernet Group Number and the at least one Ethernet PHY.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: December 10, 2019
    Assignee: Infinera Corp.
    Inventors: Iftekhar Hussain, Radhakrishna Valiveti, Khuzema Pithewan
  • Patent number: 10425252
    Abstract: Systems and methods are disclosed including a method comprising: receiving, with a controller having a computer processor, a preservation status input from a user indicative of whether or not to preserve a virtual local area network (VLAN) tag in a header of a data packet transmitted within an Ethernet local area network (E-LAN), the VLAN tag identifying at least one of customer information and service provider information for the data packet in the E-LAN, wherein the E-LAN comprises network devices having physical ports and is configured to allow multiple customers use of an individual physical port; determining a scalable network-wide service configuration model having multiple predetermined rules for automatically configuring the physical ports of the network devices for the E-LAN based on the preservation status input from the user; and configuring automatically, with the controller, the physical ports of the network devices using the predetermined rules of the configuration model.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: September 24, 2019
    Assignee: Infinera Corp.
    Inventors: Iftekhar Hussain, Snigdho C. Bardalai, Krish Verma, Murugan Rajagopal
  • Publication number: 20150333860
    Abstract: A device receives a modulation format and a baud rate for transmission of an optical signal, and generates optical signals based on the modulation format and the baud rate. The device generates quadrature-delay-interferometer signals based on the optical signal, the modulation format, and the baud rate, and generates a particular optical signal with a particular wavelength for the modulation format and the baud rate. The device determines whether a point of the quadrature-delay-interferometer signals is associated with the particular wavelength of the particular optical signal, and sets or adjusts the particular wavelength of the particular optical signal for the modulation format and the baud rate based on whether a point of the quadrature-delay-interferometer signals is associated with the particular wavelength of the particular optical signal.
    Type: Application
    Filed: December 27, 2013
    Publication date: November 19, 2015
    Applicant: Infinera Corp.
    Inventor: Jeffrey T. RAHN
  • Publication number: 20150188641
    Abstract: A digital signal processor (DSP), may identify symbol values associated with a 5 quadrature amplitude modulation (5QAM) signal. The DSP may determine a first bit set based on the symbol values and a first particular bit value. The DSP may determine a second bit set based on the symbol values and a second particular bit value. The DSP may compute a first distance based on the first bit set and the symbol values. The DSP may compute a second distance based on the second bit set and the symbol values. The DSP may determine that the first distance is less than the second distance. The first distance being less than the second distance may indicate that the first bit set is a correctly decoded bit set. The DSP may provide an output associated with the correctly decoded bit set.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 2, 2015
    Applicant: Infinera Corp.
    Inventors: Ahmed AWADALLA, Han Sun, Kuang-Tsan Wu
  • Publication number: 20150188658
    Abstract: An optical device receives a modulation format and a baud rate for transmission of an optical signal with multiple subcarrier signals, and generates the optical signal based on the modulation format and the baud rate. The optical device generates a dual-etalon response based on the optical signal, the modulation format, and the baud rate, where the dual-etalon response includes multiple peaks. The optical device compares the subcarrier signals of the optical signal and the peaks of the dual-etalon response, and determines, based on the comparing, whether at least one of the subcarrier signals aligns with a peak of the dual-etalon response. The optical device locks or adjusts a wavelength of the optical signal for the modulation format and the baud rate based on whether at least one of the subcarrier signals aligns with a peak of the dual-etalon response.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: Infinera Corp.
    Inventor: Jeffrey T. RAHN
  • Publication number: 20150188642
    Abstract: An optical receiver receives an optical signal with a phase error and pilot symbols, and converts the optical signal into an electrical signal. The optical receiver identifies, based on the pilot symbols, a cycle slip due to the phase error and associated with a transition time. The optical receiver determines, based on the pilot symbols, a direction and a center of the cycle slip, and generates a rotation value based on the direction and the center. The optical receiver applies the rotation value to minimize the phase error in the electrical signal except for phase error associated with the transition time and to generate a modified electrical signal. The optical receiver generates an erase signal based on the transition time and the center of the cycle slip, and uses the erase signal to minimize an effect of the phase error associated with the transition time of the cycle slip.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 2, 2015
    Applicant: Infinera Corp.
    Inventors: Han H. SUN, John D. McNicol, Kuang-Tsan Wu
  • Patent number: 9065747
    Abstract: A system having a first and second interfaces is described. At least one of the first and second interfaces has a cell engine, a first processor circuit, a second processor circuit, and a first and second transponder. The first processor circuit is coupled with the first transponder and the cell engine so as to transmit a header cell to the cell engine. The second processor circuit is coupled with the second transponder and the cell engine so as to transmit a body cell to the cell engine. The system may aggregate the processing capacity of several processor circuits to form larger capacity logical interfaces. Packets may be fragmented into a header cell including the packet header and body cells including the packet payload and then transmit and reassemble the packet. The header cells may be fully handled by the processor circuit, while body cells may be passed on without processing.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 23, 2015
    Assignee: Infinera Corp.
    Inventors: Jan Bialkowski, Charles A. Moorwood
  • Publication number: 20140186034
    Abstract: A system having a first and second interfaces is described. At least one of the first and second interfaces has a cell engine, a first processor circuit, a second processor circuit, and a first and second transponder. The first processor circuit is coupled with the first transponder and the cell engine so as to transmit a header cell to the cell engine. The second processor circuit is coupled with the second transponder and the cell engine so as to transmit a body cell to the cell engine. The system may aggregate the processing capacity of several processor circuits to form larger capacity logical interfaces. Packets may be fragmented into a header cell including the packet header and body cells including the packet payload and then transmit and reassemble the packet. The header cells may be fully handled by the processor circuit, while body cells may be passed on without processing.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: Infinera Corp.
    Inventors: Jan Bialkowski, Charles A. Moorwood
  • Publication number: 20140146663
    Abstract: Nodes and methods are disclosed for protection and restoration to protect against multiple failures for multiple paths involved for the same service in mesh networks, including, determining, by circuitry of a first node in a mesh network, a failure of a working path between the first node and a second node, wherein the second node, when triggered by the failure of the working path, switches to a protection path. Methods further include establishing through transmission of at least one signal by circuitry of the first node at least one recovery path, for example, a restored-working path, after determining the failure of the at least one working path, wherein the at least one restored-working path carries a duplicate of the data traffic transmitted on the protection path in case of failure of the protection path.
    Type: Application
    Filed: March 29, 2013
    Publication date: May 29, 2014
    Applicant: Infinera Corp.
    Inventors: Rajan Rao, Abhijit Kulkarni, Muhammad Yaaseen, Biao Lu, Mohit Misra, Anthony W. Jorgenson, Tjandra Trisno, Yalin Wang, Khuzema Pithewan
  • Publication number: 20130308945
    Abstract: A method and system are disclosed in which a link state advertisement message (LSA) conforming to a Generalized Multiprotocol Label Switching (GMPLS) routing protocol is generated and transmitted. The LSA is associated with a TE Link between a transmit node and a receive node in a network. The transmit node supplies a plurality of optical signals, each of which has a plurality of frequencies, the frequencies being allocated among a plurality of spectral portions such that the plurality of spectral portions are grouped into a plurality of frequency slots. The LSA may include information indicative of a number of spectral portions, e.g., spectral slices, which correspond to frequencies of selected ones of the plurality of optical signals, said selected ones of the plurality of optical signals being available to carry data from the transmit node to the receive node.
    Type: Application
    Filed: November 14, 2012
    Publication date: November 21, 2013
    Applicant: Infinera Corp.
    Inventor: Infinera Corp.
  • Publication number: 20130294228
    Abstract: Nodes and methods are disclosed, including, circuitry of a source node in a mesh network retrieving information indicative of network topology; identifying a working path from the source node to a destination node; identifying potential protection segments of the working path, wherein a potential protection segment has at least one disjoint protection path available for the segment; creating a hypothetical network topology comprising the nodes of the working path and hypothetical links between the nodes, wherein the hypothetical links represents potential protection segments identified, and the links are assigned a weight; executing a Shortest Path Algorithm on the hypothetical network topology; identifying as optimal segments the potential protection segments represented by the hypothetical links determined as being in the shortest path by the Shortest Path Algorithm; generating and transmitting a message communicating need for resources in case of failure of the optimal segments.
    Type: Application
    Filed: October 30, 2012
    Publication date: November 7, 2013
    Applicant: Infinera Corp.
    Inventors: Satyajeet S. Ahuja, Rajan Rao, Biao Lu