Patents Assigned to Initio Corporation
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Patent number: 8519746Abstract: A conversion circuit includes a super source follower circuit configured to lower an impedance of a first node. A digital control circuit is configured to adjust a current at the first node based on a current through the super source follower. An output transistor has a gate configured to receive a first signal. A drain of the output transistor is coupled to a first node, and a source of the output transistor is configured to output an output current based on a voltage of the first signal.Type: GrantFiled: September 23, 2011Date of Patent: August 27, 2013Assignee: Initio CorporationInventors: Wei Wang, Haiming Tang, Zhenchang Du
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Patent number: 8487682Abstract: A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.Type: GrantFiled: August 11, 2011Date of Patent: July 16, 2013Assignee: Initio CorporationInventors: Zhenchang Du, Haiming Tang, Wei Wang
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Publication number: 20130076403Abstract: A conversion circuit includes a super source follower circuit configured to lower an impedance of a first node. A digital control circuit is configured to adjust a current at the first node based on a current through the super source follower. An output transistor has a gate configured to receive a first signal. A drain of the output transistor is coupled to a first node, and a source of the output transistor is configured to output an output current based on a voltage of the first signal.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: INITIO CORPORATIONInventors: Wei Wang, Haiming Tang, Zhenchang Du
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Patent number: 8384438Abstract: A conversion circuit includes a first inverter having an input node configured to receive a single-ended signal and second and third inverters each having respective inputs coupled to an output of the first inverter. A fourth inverter has an input coupled to an output of the second inverter and has an output coupled to a first node. A fifth inverter has an input coupled to the first node and an output coupled to a second node to which an output of the third inverter is coupled. Sixth and seventh inverters are configured to respectively output a differential signal based on the single-ended signal. The sixth inverter has an input coupled to the first node, and the seventh inverter has an input coupled to the second node.Type: GrantFiled: August 11, 2011Date of Patent: February 26, 2013Assignee: Initio CorporationInventors: Zhenchang Du, Haiming Tang, Wei Wang
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Publication number: 20130038350Abstract: A conversion circuit includes a first inverter having an input node configured to receive a single-ended signal and second and third inverters each having respective inputs coupled to an output of the first inverter. A fourth inverter has an input coupled to an output of the second inverter and has an output coupled to a first node. A fifth inverter has an input coupled to the first node and an output coupled to a second node to which an output of the third inverter is coupled. Sixth and seventh inverters are configured to respectively output a differential signal based on the single-ended signal. The sixth inverter has an input coupled to the first node, and the seventh inverter has an input coupled to the second node.Type: ApplicationFiled: August 11, 2011Publication date: February 14, 2013Applicant: INITIO CORPORATIONInventors: Zhenchang DU, Haiming TANG, Wei WANG
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Publication number: 20130038370Abstract: A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.Type: ApplicationFiled: August 11, 2011Publication date: February 14, 2013Applicant: INITIO CORPORATIONInventors: Zhenchang DU, Haiming TANG, Wei WANG
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Patent number: 8285919Abstract: In some embodiments, a memory controller includes a plurality of processors of a first type and a processor of a second type coupled to the processors of the first type. Each of the plurality of processors of the first type is configured to determine a bad block rate of a memory channel of a solid state memory device to which it is configured to be coupled. The processor of the second type is configured to receive the bad block data rates from each of the plurality of processors of the first type and to report one of a total capacity or a bad block rate of the solid state memory device to a host device. The total capacity and the bad block rate of the solid state memory device are based on the bad block rates received from each of the plurality of processors of the first type.Type: GrantFiled: January 26, 2010Date of Patent: October 9, 2012Assignee: Initio CorporationInventors: Jianjun Luo, ChuanJen Tsu
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Patent number: 8244961Abstract: In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.Type: GrantFiled: May 19, 2009Date of Patent: August 14, 2012Assignee: Initio CorporationInventors: Jianjun Luo, ChuanJen Tsu
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Patent number: 8151038Abstract: An integrated circuit includes a first serial advanced technology attachment (SATA) channel, a plurality of second SATA channels, and a channel multiplier. The first SATA channel is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of SATA channels is configured to be coupled to a respective separate memory device channel. The channel multiplier is configured to couple the first SATA channel to each of the plurality of second SATA channels.Type: GrantFiled: May 19, 2009Date of Patent: April 3, 2012Assignee: Initio CorporationInventors: Jianjun Luo, ChuanJen Tsu, Jui Chuan Liang, Minhorng Ko
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Patent number: 7970978Abstract: In one embodiment, a data storage system, includes a controller and a plurality of solid state memory devices each including at least one memory unit. The controller includes a data interface of a first type, a data interface of a second type, and a first serial data bus. Each of the data interfaces of the first and second types is configured to be coupled to a corresponding data interface of a host device. The first serial data bus is coupled to each of the data interfaces of the first and second types and to the plurality of solid state memory devices. The controller is configured to manage data flow between the plurality of solid state memory devices and the host device through the data interfaces of the first and second types.Type: GrantFiled: May 19, 2009Date of Patent: June 28, 2011Assignee: Initio CorporationInventors: Jianjun Luo, ChuanJen Tsu, Minhorng Ko
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Publication number: 20100122022Abstract: In some embodiments, a memory controller includes a plurality of processors of a first type and a processor of a second type coupled to the processors of the first type. Each of the plurality of processors of the first type is configured to determine a bad block rate of a memory channel of a solid state memory device to which it is configured to be coupled. The processor of the second type is configured to receive the bad block data rates from each of the plurality of processors of the first type and to report one of a total capacity or a bad block rate of the solid state memory device to a host device. The total capacity and the bad block rate of the solid state memory device are based on the bad block rates received from each of the plurality of processors of the first type.Type: ApplicationFiled: January 26, 2010Publication date: May 13, 2010Applicant: INITIO CORPORATIONInventors: Jianjun LUO, ChuanJen TSU
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Publication number: 20090300258Abstract: An integrated circuit includes a first serial advanced technology attachment (SATA) channel, a plurality of second SATA channels, and a channel multiplier. The first SATA channel is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of SATA channels is configured to be coupled to a respective separate memory device channel. The channel multiplier is configured to couple the first SATA channel to each of the plurality of second SATA channels.Type: ApplicationFiled: May 19, 2009Publication date: December 3, 2009Applicant: INITIO CORPORATIONInventors: Jianjun LUO, ChuanJen TSU, Jui Chuan LIANG, Minhorng KO
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Publication number: 20090300259Abstract: In one embodiment, a data storage system, includes a controller and a plurality of solid state memory devices each including at least one memory unit. The controller includes a data interface of a first type, a data interface of a second type, and a first serial data bus. Each of the data interfaces of the first and second types is configured to be coupled to a corresponding data interface of a host device. The first serial data bus is coupled to each of the data interfaces of the first and second types and to the plurality of solid state memory devices. The controller is configured to manage data flow between the plurality of solid state memory devices and the host device through the data interfaces of the first and second types.Type: ApplicationFiled: May 19, 2009Publication date: December 3, 2009Applicant: INITIO CORPORATIONInventors: Jianjun LUO, ChuanJen TSU, Minhorng KO
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Publication number: 20090300274Abstract: In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.Type: ApplicationFiled: May 19, 2009Publication date: December 3, 2009Applicant: INITIO CORPORATIONInventors: Jianjun LUO, ChuanJen TSU