Abstract: A bootstrap driver circuit is used asynchronously in a static RAM. A capacitor is coupled between second and third nodes, and a charge pump is coupled to provide charge to the second node. Address bits can be applied to the gates of respective transistors whose drains form a common node coupled to the source of a low impedance transistor whose drain is coupled to a first node. An inverter is coupled to the common node for applying a delayed input signal to the gates of first and second enhancement mode transistors. This provides a discharge path for the third node in response to a low level memory address signal thereby to maintain a differential voltage across the bootstrap capacitor. Also disclosed is an input protection circuit when the bootstrap driver is used as a chip select buffer. A timing circuit receives an input signal and develops a first signal and a delayed signal, both of which are applied to the bootstrap driver.

Abstract: A low power I/O scheme is described which is particularly useful in wide word semiconductor memories which include redundant memory cells as well as regular memory cells. In the present scheme, conventional load transistors for a main data bus are turned off during all write operations to conserve power. In addition, predata lines which carry data between memory cells and the main data buss include load transistors that are turned off during normal read or write operations to conserve additional power, and turned on during spare read or write operations to preserve the stability of unselected regular cells. The predata lines are also preferably held above ground potential during read or write operations to prevent conduction of deselected column select transistors.

Abstract: An improved process in making a polysilicon resistor suitable for use as a load resistor in a static memory wherein after the doping of the polysilicon, the device is annealed by exposing it to a rapid increase of ambient temperature (up to between 900.degree. and 1200.degree. C.), maintaining the high ambient temperature for a controlled time (about 5 seconds) and then lowering the ambient temperature at a rapid rate. This decreases resistance by one order of magnitude and significantly decreases the temperature activation energy of the resistor. This permits static memory cells to retain data even though the cell has high leakage currents, thereby improving final test yields.

Abstract: A bootstrap driver circuit is used asynchronously in a static RAM. A capacitor is coupled between second and third nodes, and a charge pump is coupled to provide charge to the second node. Address bits can be applied to the gates of respective transistors whose drains form a common node coupled to the source of a low impedance transistor whose drain is coupled to a first node. An inverter is coupled to the common node for applying a delayed input signal to the gates of first and second enhancement mode transistors. This provides a discharge path for the third node in response to a low level memory address signal thereby to maintain a differential voltage across the bootstrap capacitor. Also disclosed is an input protection circuit when the bootstrap driver is used as a chip select buffer. A timing circuit receives an input signal and develops a first signal and a delayed signal, both of which are applied to the bootstrap driver.

Abstract: A circuit is described for precharging and equilibrating the bit lines in a semiconductor memory. The circuit includes a pair of precharging transistors, each coupled between its own bit line and a common node, and each adapted to receive a precharging pulse at its gate. A transistor circuit is coupled to the common node to establish thereat a variable operating potential such that when the precharging pulse occurs, one of the precharging transistors conducts to raise its bit line to a precharge potential while simultaneously reducing the operating potential at the common node. The lower voltage at the common node permits the other precharging transistor to conduct so that its bit line is precharged and both bit lines are equilibrated through the conducting transistors.

Abstract: The invented technique permits the gate length to equal the channel length: source/drain regions are self-aligned and non-overlapping with respect to their gate electrode. The non-overlapping feature, along with other optimized device characteristics, are generally provided by defining a gate electrode over a substrate, forming an implant mask of dielectric, for example, on the sides of the gate electrode, and implanting a source/drain region such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode and the implanted regions. The source/drain region is then heat driven until its side edge is substantially aligned with the edge of the gate electrode. Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.

Abstract: A single polycrystalline silicon configuration for a memory cell in a static MOS RAM and a method of fabricating the same are described. Three conductivity regions are utilized to form each memory cell. A first conductivity region is formed in the substrate to create a buried ground line and sources and drains of transistors. A second conductivity region is formed within an insulation layer and above the first conductivity region to create a word line, gate regions of the transistors, load resistors, and a power supply line. The power supply line is oriented directly above and parallel to the ground line. A third conductivity region is formed on the surface of the insulation layer to create data lines. The number of process steps and the size of the memory cell are reduced by this configuration.

Abstract: A single polycrystalline silicone configuration for a memory cell in a static MOS RAM and a method of fabricating the same are described. Three conductivity regions are utilized to form each memory cell. A first conductivity region is formed in the substrate to create a buried ground line and sources and drains of transistors. A second conductivity region is formed within an insulation layer and above the first conductivity region to create a word line, gate regions of the transistors, load resistors, and a power supply line. The power supply line is oriented directly above and parallel to the ground line. A third conductivity region is formed on the surface of the insulation layer to create data lines. The number of process steps and the size of the memory cell are reduced by this configuration.

Abstract: A redundancy system is described for a high speed, wide-word semiconductor memory having first and second arrays of regular memory cells. The system includes a plurality of spare columns of cells, half of which are located adjacent the first array and half of which are located adjacent the second array. The number of spare columns which are adjacent each array is equal to the number of regular columns which are simultaneously selectable by an address input. Circuitry is included for responding to an incoming address representative of a defective regular cell for selecting half the spare columns in the first array in lieu of the regular addressed columns therein, and for selecting half the spare columns in the second array in lieu of the addressed regular columns therein.

Abstract: A trigger circuit is described for use in an MOS clock generator. The clock generator is the type which uses a conventional double bootstrapping circuit coupled to a control transistor to develop a high level clock output signal. The trigger circuit preconditions the control transistor to facilitate proper bootstrapping operation. Included in the trigger circuit is a plurality of interconnected transistors which respond to a pre-charge signal and then a warmup signal for turning the control transistor off and then for establishing selected potentials at the electrodes of the control transistor to precondition it for bootstrapping. In response to a subsequent trigger signal, the trigger circuit enables the control transistor for developing a high level clock output signal.

Abstract: A process is described for anisotropically etching semiconductor products which include a lower dielectric layer, an intermediate polysilicon layer, and an upper silicide layer such as titanium silicide. A pattern-defining layer will normally overlie the silicide layer to define target areas to be etched. In a first step, the silicide is etched through using Freon 115 chloro, pentafluoroethane (C.sub.2 ClF.sub.5) in a plasma etching chamber conditioned to provide a reactive ion etch. The etch is completed in the same chamber using a second gas which includes an amount of Cl.sub.2 selected to etch anisotropically through the polysilicon layer without substantially etching the dielectric layer. Preferably, both etches occur after covering inner surfaces of the etching chamber with a material which releases molecules of the character included in the pattern-defining layer, such as Kapton, a polymide, in the disclosed example.

Abstract: An improved substrate bias generator for MOS integrated circuits is described. The generator includes circuitry for generating two trains of periodic pulses which are approximately phase opposite, one of the pulse trains being slightly delayed as compared to the other pulse train. The two pulse trains are applied to a pumping circuit which generates a target voltage and initially transfers a positive charge into the substrate, and thereafter transfers a positive charge out of the substrate. The positive charge transferred out of the substrate is greater than the positive charge transferred into the substrate when the absolute value of the potential on the substrate is less than the target voltage. Otherwise, a net positive charge is transferred into the substrate. In this manner, the absolute value of the potential on the substrate is driven towards the target voltage.

Abstract: A method is described for fabricating MOS devices of the type found in very large scale integrated circuits. According to the method described herein, various gate oxides and insulating layers are fabricated independently of each other in order to independently tailor their thicknesses and thereby provide improved isolation between gate electrodes and interconnects, and independently controllable operating characteristics for multiple gate electrode structures. The fabrication of a dynamic RAM memory cell, an overlapping gate CCD device and a self-aligned MNOS transistor cell are described using the disclosed method.

Abstract: A redundancy scheme is described for replacing defective main memory cells in a dynamic RAM with spare memory cells. The spare cells are arranged in groups of spare rows and spare columns of memory cells such that a plurality of groups of spare rows and columns of cells are substituted for defective main rows and columns of cells so as to repair relatively large defects which impair adjacent rows and columns of main memory cells. In the preferred embodiment, the RAM includes a plurality of address buffers, each of which receives an incoming row address bit and then an incoming column address bit for sequentially outputting row and column address data. Associated with each buffer is a store for a defective row address, a store for a defective column address, and a comparator. The stores retain defective memory cell addresses which the comparator sequentially compares against the address data sequentially output by the buffer.

Abstract: A static RAM (random access memory) is described wherein fully asynchronous active equilibration and precharging of the RAM's bit lines provides improved memory access time and lower active power dissipation. In the preferred embodiment, each change in the memory's row address is sensed for developing a clock pulse of a controlled duration. The clock pulse is received by a group of equilibrating transistors and a group of precharging transistors which are coupled to the memory's bit lines. When the clock pulse occurs, all the abovementioned transistors conduct to effect simultaneous equilibration and pre-charging of the bit lines.

Abstract: A folded bit line-shared sense amplifier arrangement is described for sensing the logic state of an accessed memory cell in a dynamic MOS random access memory. In the preferred embodiment, a shared sense amplifier is positioned between and coupled to first and second bit lines via first and second isolation transistors. The same shared sense amplifier is also positioned between and coupled to third and fourth bit lines via third and fourth isolation transistors. When the state of an accessed memory cell is to be sensed, its memory cell capacitor is coupled to a selected bit line and a dummy cell capacitor is coupled to the bit line adjacent the selected bit line. A decoding circuit selectively activates the shared sense amplifier to sense a difference in voltage between the selected bit line and its adjacent bit line so as to determine the logic state associated with the accessed memory cell. Then, the sense amplifier latches into this logic state for reading by the input/output buss lines.

Abstract: A redundancy scheme is described for use with an MOS memory having a main array of memory cells, and a plurality of spare memory cells. Typically, each memory cell is tested for operability by a conventional probe test. When a defective memory cell is found, an on-chip address controller responds to the probe test finding a defective cell by permanently storing and rendering continuously available a fully asynchronous electrical indication of the address of the defective cell. The address controller compares its stored data with memory cell information received during normal memory operation, and generates a control signal indicative of the receipt of an address which corresponds to a defective cell. A spare cell selector responds to the control signal by electrically accessing a spare memory cell and by prohibiting access of the defective memory cell.

Abstract: A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for storing data derived from successive locations in memory, and a corresponding plurality of serially coupled decoders, each associated with one of the data latches. In response to an address input, one decoder is enabled for causing its associated data latch to output its stored data to the data buss. The latter decoder then disables itself and enables the next decoder so that a second latch outputs its stored data. The process continues with each decoder disabling itself and enabling the next decoder so that the data latches are caused to sequentially output their stored data.

Abstract: A substrate bias generator for an integrated circuit, metal-oxide-semiconductor (MOS) random access memory (RAM) is described. The on-chip generator includes two input terminals for receiving first and second trains of periodic pulses. The periodic pulses have the same frequency and are phase synchronized. However, the first train of pulses has a greater duty cycle than the second train of pulses. Amplitude transitions associated with the first and second trains of pulses are capacitively coupled to first and second nodes, respectively. A pair of transistors are coupled to the nodes, one transistor for clamping the first node to ground when the second node receives a positive-going voltage transition, and another transistor for selectively coupling amplitude transitions from the first node to the second node. In operation, both nodes are driven more negative with each successive incoming pulse until they reach about -5 volts for the case in which the amplitude of the incoming pulses is 5 volts.