Abstract: An omnibus quasi-hydrosystem is disclosed. The omnibus quasi-hydrosystem includes a module base, at least two channel switching members mounted in the module base, at least two inlets formed in the module base and at least two outlets formed in the module base. The inlets allow fluid entering into the omnibus quasi-hydrosystem, the channel switching members alter the fluid path in the omnibus quasi-hydro system to a desired outlet to output the fluid. In addition, a modular omnibus quasi-hydrosystem is also disclosed herein.

Abstract: A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a P type silicon substrate, a control gate CG and a pair of electrically isolated floating gates. Plural projections are formed in the silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate extending in the row direction faces the projection and the floating gate FG1, FG2 via an insulation layer. The width W1 of the floating gate FG1, FG2 in the column direction is larger than the width W2 of the control gate CG, so the floating gate FG1, FG2 and the control gate CG can be manufactured without the self-align process.

Abstract: A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.

Abstract: The MOS type solid-state imaging device has plural pixels each of which comprises a photo-diode and a MOS transistor on a substrate. A gate electrode is formed on the channel dope layer formed in the surface of the p-type well layer. By ion implantation of n-type impurity ions via the gate electrode as the mask, the n-type source region and the drain region are formed in the region corresponding to the MOS transistor, and the n-type impurity region is also formed in the region corresponding to the photo-diode. In the well layer, a high impurity density region as a hole pocket is self-aligned to the gate electrode.

Abstract: A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.

Abstract: A method for producing a solid-state imaging device comprising a plurality of unit pixel sections, including a first unit pixel section, is provided. The method includes the steps of forming a first conductivity type well region of the first unit pixel section on a second conductivity type semiconductor layer provided on a first conductivity type semiconductor layer, the first conductivity type well region including a light receiving region for generating charges corresponding to an amount of light incident thereon and a charge transfer region capable of transferring the charges; and generating a charge accumulation region, for accumulating the charges generated in the light receiving region, in the charge transfer region. The step of forming the first conductivity type well region includes the step of implanting impurities such that the light receiving region and the charge transfer region in the first conductivity type well region have a substantially uniform impurity concentration.

Abstract: A multiple-bit cell transistor includes a P type silicon substrate, a gate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.

Abstract: A system for the optical analysis of a sample. An illumination source illuminates the sample, exciting fluorescence. The fluorescence is collected by an objective lens, which transmits the collected illumination light onto an imaging lens, which focuses the collected light onto an area array detector. Collected light rays between the objective lens and the imaging lens are parallel and pass through an emission filter. Both the objective lens and the imaging lens are positioned on a mount that allows an alternative objective or imaging lens to be positioned to collect or image the emitted light. Any objective lens/imaging lens pair is optically symmetrical, greatly reducing the optically degrading effects.

Abstract: A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.

Abstract: Disclosed is a method of storing optically generated charges by an optical signal in a solid state imaging device, which is particularly a method of storing optically generated charges by an optical signal in a solid state imaging device using a MOS image sensor of a threshold voltage modulation type, which is used for a video camera, an electronic camera, an image input camera, a scanner, a facsimile or the like.

Abstract: A transistor includes p-type semiconductor (12) including a projection (13a) having a pair of side walls (13b, 13b) facing each other, a gate insulation layer (15c), a pair of n-type source/drain regions (BL1, BL2), tunnel insulation layers (15a), a pair of floating gates (FG1, FG2), inter-polycrystalline insulation layers, and a control gate (CG). The root portion of the projection (13A), which virtually connects the source/drain regions (BL1, BL2) with a straight line, is higher in the concentration of the p-type impurity than the other portion. A delete voltage for deleting charges stored in the floating gate (FG) is applied between the control gate (CG) and the source/drain region (BL1, BL2), so that a delete current flows toward the control gate (CG) or the source/drain region (BL1, BL2), the charges stored being deleted.

Abstract: A multiple-bit transistor includes P type semiconductor including a projection, a gate insulation layer, a pair of N type source/drain regions, tunnel insulation layers, a pair of floating gates, inter-polycrystalline insulation layers, and a control gate. The root portion of the projection, which is defined by a straight line virtually connecting the source/drain regions, is higher in the concentration of the P type impurity than the other portion. A potential difference for write-in is set up between the source/drain regions while a write voltage is applied to the control gate, thereby causing electrons to be ballistically injected into at least one of the floating gates.

Abstract: The invention is a method and apparatus to extend the signal range of a digital image beyond the nominal sensor or data format range. The method and apparatus automatically acquires a scaled series of source data, applies noise reduction to the source data, and constructs a scaled composite with usable signal ranges greater than that of the individual data sources. Applied to digital images, the invention permits presentation and analysis of all signals from a subject in a single composite or an image resulting from the method and apparatus of the present invention. The present invention overcomes two defects in prior art systems: increased noise in the resultant composite image arising from rescaling of component images and dependence on evaluating image content to determine image scaling. Because this invention can be automated, it can be applied in numerous fields requiring high throughput.

Abstract: A system for optical detection of kinetic samples. The system includes a dual set of detectors linked to a single processor. The time of signal integration is different for each detector, allowing one detector to have a higher sensitivity by integrating over a longer time period while the second detector using shorter integration periods is able to measure kinetic events.

Abstract: A probe (1A) has a cutting blade portion (2) at a tip end that is brought into contact with a pad electrode (5). The cutting blade has a cutting edge that is in a plane parallel to the direction of sliding of the blade over a pad electrode, when the edge is brought into contact with the electrode. The cutting edge (2a) has a sloping or curved shape that comes closer to the electrode from the front side to the rear side of the blade along the direction of sliding. Thus, as the cutting edge (2a) cuts into an insulating coating (7) formed on the surface of the electrode, the probe ensures satisfactory electrical conduction between the probe (1A) and the electrode because it cuts through the coating without causing swarfs.

Abstract: A multiple-bit cell transistor includes a P type silicon substrate, agate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.

Abstract: A multiple-bit cell transistor includes a P type silicon substrate, agate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.

Abstract: Disclosed is a solid state imaging device, comprising a unit pixel 101 including a photo diode 111 and a MOS transistor 112 for optical signal detection provided with a high-density buried layer 25 for storing optically generated charges generated by light irradiation in the photo diode 111, a vertical scanning signal driving scanning circuit 102 for outputting a scanning signal to a gate electrode 19, and a voltage boost scanning circuit 108 for outputting a boosted voltage higher than a power source voltage to a source region 16. In this case, a boosted voltage is applied from the voltage boost scanning circuit 108 to the source region 16, and the optically generated charges stored in the high-density buried layer 25 are swept out from the high-density buried layer 25 by a source voltage and a gate voltage risen by the boosted voltage.

Abstract: A solid-state imaging device is provided, which is capable of increasing an S/N ratio while enhancing a dynamic range, when a photoelectric signal is converted into a digital signal. This solid-state imaging device comprises: a plurality of photoelectric conversion devices arrayed in rows and columns, each of the photoelectric conversion devices converting an optical signal into an electric signal and outputting a first signal voltage; a difference signal generation circuit provided for each column, for sequentially inputting the first signal voltage and a second signal voltage obtained by initializing the photoelectric conversion devices, thereafter converting the first signal voltage and the second signal voltage into charges, generating a difference signal therebetween, and then outputting the difference signal after adjusting a gain according to a level of the difference signal; and an analog/digital conversion circuit connected to the output of the difference signal generation circuit.

Abstract: The invention is a method and apparatus to extend the signal range of a digital image beyond the nominal sensor or data format range. The method and apparatus automatically acquires a scaled series of source data, applies noise reduction to the source data, and constructs a scaled composite with usable signal ranges greater than that of the individual data sources. Applied to digital images, the invention permits presentation and analysis of all signals from a subject in a single composite or an image resulting from the method and apparatus of the present invention. The present invention overcomes two defects in prior art systems: increased noise in the resultant composite image arising from rescaling of component images and dependence on evaluating image content to determine image scaling. Because this invention can be automated, it can be applied in numerous fields requiring high throughput.