Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.

Abstract: A storage device is configured to communicate with a host device over a Bluetooth connection. The storage device includes a flash memory, a processor, and a Bluetooth controller. The memory stores at least one permission for determining access to the memory. The processor manages access to the memory, independently of the host device, based on a comparison of a request at the removable storage device to access the memory to at least one permission. The comparison is independent, requiring no management by an operating system of the host device, such that if the at least one permission includes a particular access type that matches the access requested in the request, the processor provides access to the memory.

Abstract: A storage device is configured to communicate with a host device over a Bluetooth connection. The storage device includes a flash memory, a processor, and a Bluetooth controller. The memory stores at least one permission for determining access to the memory. The processor manages access to the memory, independently of the host device, based on a comparison of a request at the removable storage device to access the memory to at least one permission. The comparison is independent, requiring no management by an operating system of the host device, such that if the at least one permission includes a particular access type that matches the access requested in the request, the processor provides access to the memory.

Abstract: A non-volatile memory is divided into logical zones by the card controller in order reduce the size of the data structures it uses for address translation. Zone boundaries are adjusted to accommodate defects allowed by memory test to improve card yields and to adjust boundaries in the field to extend the usable lifetime of the card. Firmware scans for the presence of defective blocks on the card. Once the locations of these blocks are known, the firmware calculates the zone boundaries in such a way that good blocks are equally distributed among the zones. Since the number of good blocks meets the card test criteria by the memory test criteria, defects will reduce card yield fallout. The controller can perform dynamic boundary adjustments. When defects occur, the controller can perform the analysis again and, if needed, redistributes the zone boundaries, moving any user data.

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.