Patents Assigned to Innovative Silicon S.A.
-
Patent number: 7359229Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns.Type: GrantFiled: March 2, 2007Date of Patent: April 15, 2008Assignee: Innovative Silicon S.A.Inventors: Richard Ferrant, Serguei Okhonin, Eric Carman, Michel Bron
-
Patent number: 7355916Abstract: There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by sensing circuitry to sense the data state of a memory cell during a read operation of one or more memory cells. The control, adjustment, determination and/or modification of the reference current levels may be implemented using many different, distinct and/or diverse techniques and circuitry, including both analog and digital techniques and circuitry.Type: GrantFiled: September 5, 2006Date of Patent: April 8, 2008Assignee: Innovative Silicon S.A.Inventor: Philippe Bauser
-
Patent number: 7342842Abstract: A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.Type: GrantFiled: January 5, 2007Date of Patent: March 11, 2008Assignee: Innovative Silicon, S.A.Inventors: Pierre Fazan, Serguei Okhonin
-
Patent number: 7335934Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, integrated circuit device includes memory portion having, for example, PD or FD SOI memory cells, and logic portion having, for example, high performance transistors, such as Fin-FET, multiple gate transistors, and/or non-high performance transistors (such as single gate transistors that do not possess the performance characteristics of the high performance transistors).Type: GrantFiled: July 2, 2004Date of Patent: February 26, 2008Assignee: Innovative Silicon S.A.Inventor: Pierre Fazan
-
Patent number: 7301838Abstract: A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is relatively compact and pitched to the array of memory cells such that a row of data may be read, sampled and/or sensed during a read operation. In this regard, an entire row of memory cells may be accessed and read during one operation which, relative to at least architecture employing multiplexer circuitry, may minimize, enhance and/or improve read latency and read access time, memory cell disturbance and/or simplify the control of the sense amplifier circuitry and access thereof. The sense amplifier circuitry may include write back circuitry to modify or “re-store” the data read, sampled and/or sensed during a read operation and/or a refresh operation in the context of a DRAM array.Type: GrantFiled: December 12, 2005Date of Patent: November 27, 2007Assignee: Innovative Silicon S.A.Inventors: William Kenneth Waller, Eric Carman
-
Patent number: 7301803Abstract: A method and a device for the coding and decoding of an information symbol for transmission over a transmission channel or a received signal value is described and illustrated, whereby a channel symbol used for coding is selected from at least two available channel symbols by means of a pre-calculated expected received signal value. The pre-calculation is achieved, based on the echo properties of the transmission channel and transmission values already sent. A pre-coding method with low receiver-side calculation requirement is thus prepared, whereby the information symbol can be transmitted by means of various channel symbols and thus various transmission values can also be transmitted. The possible selections may be used for minimization of the transmission energy and/or to achieve a minimal disturbance or even a constructive effect through the inter-symbol interference occurring on transmission.Type: GrantFiled: December 15, 2005Date of Patent: November 27, 2007Assignee: Innovative Silicon S.A.Inventors: Serguei Okhonin, Mikhail Nagoga
-
Patent number: 7280399Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.Type: GrantFiled: August 11, 2005Date of Patent: October 9, 2007Assignee: Innovative Silicon S.A.Inventors: Pierre Fazan, Serguei Okhonin
-
Patent number: 7251164Abstract: An integrated circuit device comprising a memory cell array including a plurality of memory cells wherein each memory cell includes at least one electrically floating body transistor having source, drain and a body regions, wherein the body region is electrically floating and disposed between the source and drain regions; a gate is disposed over the body region. Each memory cell includes a first data state representative of a first charge in the body region and a second data state representative of a second charge in the body region. The integrated circuit device further includes operating characteristics adjustment circuitry, coupled to the memory cell array, to adjust one or more operating or response characteristics of one or more memory cells to improve the uniformity of operation/response characteristics of the memory cells of the memory cell array relative to the other memory cells of the array.Type: GrantFiled: October 11, 2005Date of Patent: July 31, 2007Assignee: Innovative Silicon S.A.Inventors: Serguei Okhonin, Mikhail Nagoga
-
Patent number: 7239549Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.Type: GrantFiled: May 19, 2005Date of Patent: July 3, 2007Assignee: Innovative Silicon S.A.Inventors: Pierre Fazan, Serguei Okhonin
-
Patent number: 7187581Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns.Type: GrantFiled: March 14, 2005Date of Patent: March 6, 2007Assignee: Innovative Silicon S.A.Inventors: Richard Ferrant, Serguei Okhonin, Eric Carman, Michel Bron
-
Low power programming technique for a floating body memory transistor, memory cell, and memory array
Patent number: 7184298Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.Type: GrantFiled: September 15, 2004Date of Patent: February 27, 2007Assignee: Innovative Silicon S.A.Inventors: Pierre Fazan, Serguei Okhonin -
Low power programming technique for a floating body memory transistor, memory cell, and memory array
Patent number: 7177175Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.Type: GrantFiled: January 17, 2006Date of Patent: February 13, 2007Assignee: Innovative Silicon S.A.Inventors: Pierre Fazan, Serguei Okhonin -
Patent number: 7170807Abstract: A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.Type: GrantFiled: February 1, 2005Date of Patent: January 30, 2007Assignee: Innovative Silicon S.A.Inventors: Pierre Fazan, Serguei Okhonin
-
Patent number: 7085153Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell.Type: GrantFiled: April 22, 2004Date of Patent: August 1, 2006Assignee: Innovative Silicon S.A.Inventors: Richard Ferrant, Serguei Okhonin, Eric Carman, Michel Bron
-
Patent number: 7085156Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns.Type: GrantFiled: April 1, 2005Date of Patent: August 1, 2006Assignee: Innovative Silicon S.A.Inventors: Richard Ferrant, Serguei Okhonin, Eric Carman, Michel Bron
-
Patent number: 7061050Abstract: A semiconductor device such as a DPAM memory device is disclosed. A, Substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semi-conductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).Type: GrantFiled: March 17, 2003Date of Patent: June 13, 2006Assignee: Innovative Silicon S.A.Inventors: Pierre Fazan, Serguei Okhonin
-
Patent number: 6980461Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is a technique and circuitry for reading data that is stored in memory cells. In one embodiment of this aspect, the present invention is a technique and circuitry for generating a reference current that is used, in conjunction with a sense amplifier, to read data that is stored in memory cells of a DRAM device. The technique and circuitry for generating a reference current may be implemented using an analog configuration, a digital configuration, and/or combinations of analog and digital configurations.Type: GrantFiled: February 18, 2005Date of Patent: December 27, 2005Assignee: Innovative Silicon S.A.Inventors: Lionel Portmann, Maher Kayal, Marc Pastre, Marija Blagojevic, Michel Declercq
-
Patent number: 6937516Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.Type: GrantFiled: October 28, 2003Date of Patent: August 30, 2005Assignee: Innovative Silicon S.A.Inventors: Pierre Fazan, Serguei Okhonin
-
Patent number: 6934186Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.Type: GrantFiled: December 19, 2003Date of Patent: August 23, 2005Assignee: Innovative Silicon S.A.Inventors: Pierre Fazan, Serguei Okhonin
-
Patent number: 6930918Abstract: A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.Type: GrantFiled: December 1, 2003Date of Patent: August 16, 2005Assignee: Innovative Silicon S.A.Inventors: Pierre Fazan, Serguei Okhonin