Abstract: A method of testing a device includes monitoring an output of the device, wherein the output is generated by the device in response to an applied test command; and resolving the output into atomic operations, wherein the atomic operations are substantially the smallest constituent operations which are substantially independent of the device. The method is used to provide a simple, comprehensive test environment that effectively tests 1394a and 1394-1995 designs, for example, in Verilog. The test environment contains rules which completely characterize the behavior of different 1394 bus protocols as defined by the IEEE specifications. The test environment provides portability between different devices under test and between different protocols, automated closed-loop reconciliation of test commands and protocol requirements, topology independence, and out-of-order execution of instructions or relative sequencing.

Abstract: Two on-chip buses (OCBs) having respective standardized definitions are implemented on a multi-function system chip, with one of the OCB definitions being a subset of the other. System virtual components (VCs) are connected to the system OCB with a system virtual component interface or “bus wrapper”. “Peripheral” virtual components are connected to a peripheral OCB using respective standard interface blocks. Since the definition of the peripheral OCB is a subset of the system OCB, bridging between the two OCBs is relatively straightforward. The invention permits a “plug and play’ capability on behalf of all peripheral VC designs implemented according to the standard, such that the systems integrator may mix and match peripheral VCs without degradation of functionality or performance.

Abstract: A system and method for selective transfer of application data between storage devices in a computer system. Application data and non-application data are stored in a mass memory device. The application data and non-application data are received in a dump memory. Data in the dump memory is examined to identify the application data. A secondary address for the application data is derived. Application data from the dump memory indicated by the secondary address is received by a memory array. The application data indicated by the secondary address is parsed. Parsed application data is transferred from the memory array to dump memory. The parsed application data and the non-application data are transferred from the dump memory to the mass memory device. Finally, unexamined data is dumped from the mass memory device to the dump memory. The application data in one example represents a circuit to be simulated and the circuit could be described in a hardware description language such as VERILOG.