Abstract: A radio frequency synthesizer receives a relatively low frequency input signal and synthesizes from it a high frequency output signal whose frequency can be programmed to change in fine steps, for use e.g. in cordless telephone. The frequency synthesizer includes three linked phase locked loops with a single side band mixer in one embodiment coupling two of the phase locked loops together. This provides an output signal free of in-band frequency spurs within the spacing of two channels. The synthesizer can be integrated in a single chip with a narrowband FM modulation circuit. In spite of using a novel synthesizer to achieve monolithic integration, the user programming interface and control value equations are the industry standard format.

Abstract: In a digital communication system, analog equalization and data recovery are provided with non-linear digital feedback at the receiver, to overcome frequency domain distortion imposed by the communications channel. Digital information from the clock and data recovery circuit is non-linearly filtered and then fed back so as to modulate the threshold of a slicer which receives the signal which has been analog equalized. Thereby any shortcomings in the equalization, slicer, or clock and data recovery are overcome by adjusting the slicer threshold at each clock cycle in response to the recovered clock and data signals.

Abstract: A DC restoration circuit to correct for baseline wandering in a data receiver is provided. A voltage correction circuit is connected to the received data line to adjust the voltage level of the received data dynamically. The voltage correction circuit is controlled by a feedback circuit which includes a voltage detection circuit configured to detect the peak voltage levels or envelope of the received data. This detected level is then compared to a reference level, and the result of the comparison is used as a control signal for the voltage correction circuit.

Abstract: A dual dot clock signal generator consisting of two similar programmable phase locked loops simultaneously generates a video clock signal and a memory clock signal. Both the video clock signal and the memory clock signal may have one of several different frequencies. The generator includes circuitry which detects when one of the selected frequencies is identical to or a submultiple of the other. The comparison circuitry which detects this condition acts to change the frequency of one of the clock signals, and supplies the other clock signal in its place. Both the video clock signal generator and the memory clock signal generator are programmable via their respective internal memories, and the internal memory of the video clock signal generator carries additional information which identifies those video frequencies which are identical to or a submultiple of the frequencies available from the memory phase locked loop.

Abstract: A video dot clock generator includes a phase-locked loop (PLL) which includes a voltage controlled oscillator, a frequency divider, a phase comparator and a loop filter. The voltage controlled oscillator (VCO) is programmable to provide multiple frequency ranges for a given range of control voltages applied to the oscillator. The programming affects both the frequency range and the gain of the VCO. The phase comparator includes circuitry which simulates a predetermined minimum phase error which, when compensated for, substantially eliminates jitter in the dot clock signal. The frequency divider used in the PLL and a similar frequency divided used to generate the reference signals for the phase comparator are programmable via an internal memory which also holds programmable control signals for the VCO. The memory, in turn, may be programmed by the user to achieve desired frequency and loop again characteristics for a given application.