Abstract: Disclosed is an analog processing element (APE) for the analog processing of charge packets present in an analog signal. The APE utilizes CCD-based elements in a semi-conductor device to move and process charge packets present in an analog signal. In one embodiment, the APE provides analog processing on dimensional signals such as audio or video signals. When the APE is embodied in a semi-conductor device, it may be provided as a chip for analog pre-processing of video or audio signals such as for compression of the signal prior to digitization and use by digital processing devices. In a particular embodiment, an array of APE's, along with related circuitry provides for a pipelined Pattern Recognition Processor (PRP). The PRP may perform analog video compression at rates substantially exceeding compression rates available with current digital processing technology.

Abstract: Disclosed is an analog processing element (APE) for the analog processing of charge packets present in an analog signal. The APE utilizes CCD-based elements in a semi-conductor device to move and process charge packets present in an analog signal. In one embodiment, the APE provides analog processing on dimensional signals such as audio or video signals. When the APE is embodied in a semi-conductor device, it may be provided as a chip for analog pre-processing of video or audio signals such as for compression of the signal prior to digitization and use by digital processing devices. In a particular embodiment, an array of APE's, along with related circuitry provides for a pipelined Pattern Recognition Processor (PRP). The PRP may perform analog video compression at rates substantially exceeding compression rates available with current digital processing technology.

Abstract: A new technology in semiconductor electronics is provided wherein basic semiconductor elements (BSEs) are fabricated on the surfaces of hollow, cone-shaped and/or other planar or non-planar substrata. Photosensitive and photoemitting elements are included within each BSE capable of transmitting and receiving signals to and from external sources in a direction that is non-parallel (oblique) to the silicon surface and circuitry plane. Inter-BSE communication are also achieved via fiber optic connectors. In one embodiment, the BSEs may be assembled in an efficient arrangement whereby some number of BSEs (for example, six (6)) are located adjacent and surrounding another "polar" BSE, thereby providing for short opto-electronic connections between the polar BSE and its neighbors. In additional embodiments, a power supply may reside within the internal space of the BSE, and the interior and exterior of the BSEs are designed as opposite electrical poles, thereby providing power to the BSEs.

Abstract: A new technology in semiconductor electronics is provided wherein basic semiconductor elements (BSEs) are fabricated on the surfaces of hollow, cone-shaped and/or other planar or non-planar substrata. Photosensitive and photoemitting elements are included within each BSE capable of transmitting and receiving signals to and from external sources in a direction that is non-parallel (oblique) to the silicon surface and circuitry plane. Inter-BSE communication are also achieved via fiber optic connectors. In one embodiment, the BSEs may be assembled in an efficient arrangement whereby some numbers of BSEs (for example, six (6)) are located adjacent and surrounding another "polar" BSE, thereby providing for short opto-electronic connections between the polar BSE and its neighbors.