Patents Assigned to Integrated Materials, Incorporated
  • Patent number: 7736747
    Abstract: A method of joining two silicon members and the bonded assembly in which the members are assembled to place them into alignment across a seam. Silicon derived from silicon powder is plasma sprayed across the seam and forms a silicon coating that bonds to the silicon members on each side of the seam to thereby bond together the members. The plasma sprayed silicon may seal an underlying bond of spin-on glass or may act as the primary bond, in which case through mortise holes are preferred so that two layers of silicon are plasma sprayed on opposing ends of the mortise holes. A silicon wafer tower or boat may be the final product. The method may be used to form a ring or a tube from segments or staves arranged in a circle. Plasma spraying silicon may repair a crack or chip formed in a silicon member.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: June 15, 2010
    Assignee: Integrated Materials, Incorporated
    Inventors: James E. Boyle, Laurence D. Delaney
  • Patent number: 7736437
    Abstract: A baffled liner cover supported at the top of a liner surrounding a wafer support tower for semiconductor thermal processing. The cover may present a continuous horizontal surface for preventing particles from falling within the liner but present horizontal extending gas passageways in a baffle assembly to allow the flow of processing gas through the cover. In one embodiment, the baffle assembly includes a cup-shaped member disposed in a central aperture of a top plate having an open top, a continuous bottom, horizontal holes through the sides, and a flange around sides defining a convolute annular passage. Alternatively, the planar top plate may included slanted holes therethrough or vertical holes occupying a small fraction of the surface area. The liner and cover may be composed of quartz, silicon carbide, or preferably silicon.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: June 15, 2010
    Assignee: Integrated Materials, Incorporated
    Inventors: Tom L. Cadwell, Michael Sklyar
  • Patent number: 7736436
    Abstract: An edge ring for use in batch thermal processing of wafers supported on a vertical tower within a furnace. The edge rings are have a width approximately overlapping the periphery of the wafers and are detachably supported on the towers equally spaced between the wafer to reduce thermal edge effects. The edge rings have may have internal or external recesses to interlock with structures on or adjacent the fingers of the tower legs supporting the wafers or one or more steps formed on the lateral sides of the edge ring may slide over and then fall below a locking ledge associated with the support fingers. Preferably, the tower and edge ring and other parts of the furnace adjacent the hot zone are composed of silicon.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: June 15, 2010
    Assignee: Integrated Materials, Incorporated
    Inventors: Tom L. Cadwell, Ranaan Zehavi, Michael Sklyar
  • Publication number: 20100119817
    Abstract: A method of joining two silicon members, the adhesive used for the method, and the joined product, especially a silicon tower for supporting multiple silicon wafers. A flowable adhesive is prepared comprising silicon particles of size less than 100 ?m and preferably less than 100 nm and a silica bridging agent, such as a spin-on glass. Nano-silicon crystallites of about 20 nm size maybe formed by CVD. Larger particles maybe milled from virgin polysilicon. If necessary, a retardant such as a heavy, preferably water-insoluble alcohol such as terpineol is added to slow setting of the adhesive at room temperature. The mixture is applied to the joining areas. The silicon parts are assembled and annealed at a temperature sufficient to link the silica, preferably at 900° C. to 1100° C. for nano-silicon but higher for milled silicon.
    Type: Application
    Filed: January 11, 2010
    Publication date: May 13, 2010
    Applicant: INTEGRATED MATERIALS, INCORPORATED
    Inventors: James E. Boyle, Raanan Zehavi, Amnon Chalzel
  • Patent number: 7713355
    Abstract: A silicon shelf tower for hatch thermal processing of silicon wafers in a vertical furnace. The tower includes at least three silicon legs joined to bases and having a vertical arrangement of slots. Silicon shelves are detachably loaded by sliding them through the slots in the side legs and into the slot of the back leg. A interlocking mechanism detachably locks the shelves to the back leg while the slots in the two side legs laterally constrains the shelves. The shelves include cutouts to allow a robot paddle to load and unload wafers to the shelves. Circular holes in the shelves relieve stress and prevent wafer sticking Preferably, the shelves are formed from randomly oriented polycrystalline silicon. The shelves and towers can alternatively be made of other materials such as quartz and silicon carbide.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: May 11, 2010
    Assignee: Integrated Materials, Incorporated
    Inventors: Ranaan Zehavi, Reese Reynolds