Patents Assigned to INTEGRATED SILICON SOLUTION, INC. BEIJING
  • PVT-independent fixed delay circuit
    Patent number: 10826473
    Abstract: A PVT-independent fixed delay circuit includes a circuit structure that has a current generator and a multi-level inverter-based time delay unit. The inverter-based time delay unit has at least two NMOS transistors M5, M6, and at least two PMOS transistors M7, M8. The current generator has a circuit structure including at least two NMOS transistors M1, M2, at least two PMOS transistors M3, M4 and a resistor RS.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 3, 2020
    Assignee: INTEGRATED SILICON SOLUTION, INC. BEIJING
    Inventors: Weikang Liu, Chia Yu Lin