Abstract: A double erase control circuit is disclosed for use with an EEPROM/flash memory system wherein each memory cell can be read, erased or programmed based, in part, on the voltage level of a word line coupled to the gate of each of the memory cells. A host selectively erases flash memory cells by placing 0 VDC on the word lines and a large positive voltage (10.4 VDC to 10.8 VDC) on an array virtual ground supply (VVSS) line while the drains of the memory cells float. The voltage and current on the VVSS line are simultaneously controlled using voltage and current control circuitry that are responsive to a high erase signal that is asserted by the host during an erase operation. When the erase signal is high, the voltage control circuitry uses a comparator, a stable reference voltage (1.28 VDC) derived from a band-gap reference and a feedback loop to maintain VVSS at the target source erase voltage (i.e., 10.4 VDC to 10.8 VDC).

Abstract: A program verify and erase verify control circuit is disclosed for use with an EEPROM/flash memory system wherein each memory cell can be read, erased or programmed based, in part, on the voltage level of a word line coupled to the gate of each of the memory cells. Program operations are verified by placing a worst case (i.e., highest) read voltage on the word lines of programmed memory cells. Similarly, erase operations are verified by placing a worst case (i.e., lowest) read voltage on the word lines of erased memory cells. So that there worst case voltages are stable and reproducible, they are generated using a feedback control circuit consisting of a comparator driven by a bandgap voltage reference (+1.28 VDC ), various feedback transistors and a voltage divider network. The worst case program verification voltage (+6.4 VDC) and the worst case erase verification voltage (+4.

Abstract: A program drain voltage control system is disclosed for use within an EPROM/flash memory system wherein each memory cell is coupled in series with plural y selection transistors. When the EPROM/flash memory system is in programming mode, the control system maintains the program drain voltage of EPROM/flash memory cells being programmed at a target drain voltage (+6.1 VDC ). Drain voltage control is accomplished using a current control circuit and a voltage control circuit. The voltage control circuit uses a comparator driven by a voltage reference signal (+1.28 VDC) derived from the bandgap reference and by a voltage divider output. When the output from the voltage divider is larger than the reference voltage, the comparator output goes high, turning on a pulldown transistor, which pulls down the node where the target voltage is to be established.

Abstract: Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

Abstract: Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

Abstract: Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

Abstract: Disclosed is a byte-erasable EEPROM memory cell which utilizes a five volt external source and a voltage multiplier circuit to program and erase a floating gate by means of electron tunneling. To prevent collapse of the voltage multiplier circuit a lightly doped drain region is incorporated preventing gate modulated junction breakdown, thereby preventing collapse of the voltage multiplier circuit. In addition, current flow through the channel separating a source region and the lightly doped drain region is controlled by a portion of a control gate and the floating gate, thereby allowing a higher erased cell threshold voltage. Also disclosed is a process for forming the lightly doped drain region by using the control gate as an effective sidewall spacer.