Abstract: A method for forming flash memory units is provided. After a logic gate in a select gate PMOS transistor area is separated from a logic gate in a control gate PMOS transistor area, P-type impurities implanted into the logic gate in the select gate PMOS transistor area are diffused into an N-type floating gate polysilicon layer to convert the N-type floating gate into a P-type floating gate by a subsequent high temperature heating process, so that it is possible to successfully form a select gate PMOS transistor having a small surface channel threshold value in a 55 nm process flash memory unit, and achieve mass production. Further, a two-step growth process of the logic gate and a process for separating the logic gate can form a surface channel of the select gate PMOS transistor having a smaller threshold value without affecting the floating gate doping of the control gate PMOS transistor.

Abstract: The present disclosure relates to semiconductor devices and discloses a method for operating a flash memory. When a read operation is performed on a flash memory unit, a potential of a first control line connected to gates of select gate PMOS transistors located in a same row is switched from a positive supply voltage to 0V. Since it is not required to switch the potential from a positive voltage to a negative voltage, the power consumption of the pump circuit is significantly reduced. In addition, a read current of the flash memory unit selected for reading can accurately represent the status of the unit being read thanks to the appropriate settings of the gate oxide layer thickness and the threshold voltage of the select gate PMOS transistor. Furthermore, high-voltage devices are removed from the read path and only low-voltage devices are used, so that the reading speed can be significantly improved during the read operation.

Abstract: The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines.

Abstract: A circuit and method for controlling internal test mode entry of an Asynchronous Static Random Access Memory (ASRAM) chip wherein the circuit includes an address code comparator for detecting whether address codes inputted via an address bus of the ASRAM chip match a predefined validation code; a test mode detector for determining whether to let the ASRAM chip enter into an internal test mode; a test mode clock generator for generating a clock signal for the test mode decoder; and a test mode decoder for generating a test control signal. The circuit of the present application uses the existing pins of the ASRAM chip to input a special section of codes to trigger the ASRAM to enter into its internal test mode, thereby reducing the difficulty of testing the products.

Abstract: The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V˜12V, its bit line is applied with a voltage of 4V˜6V, and its word line is applied with a voltage of ?7V˜?10V. When a read operation is performed on the flash memory, for a sector selected for the read operation, its N-type well is applied with a VCC voltage; for a flash memory cell selected for the read operation, its bit line is applied with the VCC voltage, and its source line is applied with a voltage of 0V. When a program operation is performed on the flash memory, for a flash memory cell selected for the program operation, its bit line is applied with a voltage of VCC?6.5V˜VCC?4.5V, and its bit line is applied with a voltage of VCC+6V˜VCC+9V.

Abstract: The address transition detecting circuit includes two identical address transition detecting signal generating module, an inverter and a signal combining module. Both of the two address transition detecting signal generating modules have a unilateral delay circuit for generating an output pulse at the rising edge of the address signal and an output pulse at the falling edge of the address signal. The address transition detecting signal generating module can control the width of the two output pulses by controlling the delay times of the corresponding unilateral delay circuit. The signal combining module outputs the ATD signal having pulses at both the rising edge and falling edge of the address signal. The present application uses two unilateral delay circuits to control the width of the ATD signal at the rising edge and the falling edge of the address signal, thereby significantly preventing the width of the ATD signal from influence of the burr on the address line.

Abstract: There is disclosed an address transition detecting circuit in the present application. The address transition detecting circuit comprises two identical address transition detecting signal generating module, an inverter and a signal combining module. Both of the two address transition detecting signal generating module comprise a unilateral delay circuit for generating an output pulse at the rising edge of the address signal and an output pulse at the falling edge of the address signal. The address transition detecting signal generating module can control the width of the two output pulses by controlling the delay times of the corresponding unilateral delay circuit. The signal combining module outputs the ATD signal having pulses at both the rising edge and falling edge of the address signal.

Abstract: The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines.