Patents Assigned to Intel Coporation
  • Patent number: 11924808
    Abstract: Techniques for sidelink resource selection, reselection, and reevaluation are disclosed. An apparatus for a user equipment (UE) includes processing circuitry coupled to memory. To configure the UE for 5G-NR sidelink communications, the processing circuitry is to decode an SCI format received via a PSCCH. The SCI format includes priority information for a scheduled PSSCH transmission. RRC signaling is decoded to determine first configuration information and second configuration information. The first configuration information identifies a sensing window, and the second configuration information identifies a resource selection window. A boundary of the resource selection window is based on the priority information. A set of candidate single-slot resources is determined during the sensing window using a resource pool. A resource is selected during the resource selection window from the set of candidate single-slot resources.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Coporation
    Inventors: Andrey Chervyakov, Alexey Khoryaev, Sergey Panteleev, Mikhail Shilov, Sergey Sosnin
  • Patent number: 11455167
    Abstract: Disclosed embodiments relate to efficient complex vector multiplication. In one example, an apparatus includes execution circuitry, responsive to an instruction having fields to specify multiplier, multiplicand, and summand complex vectors, to perform two operations: first, to generate a double-even multiplicand by duplicating even elements of the specified multiplicand, and to generate a temporary vector using a fused multiply-add (FMA) circuit having A, B, and C inputs set to the specified multiplier, the double-even multiplicand, and the specified summand, respectively, and second, to generate a double-odd multiplicand by duplicating odd elements of the specified multiplicand, to generate a swapped multiplier by swapping even and odd elements of the specified multiplier, and to generate a result using a second FMA circuit having its even product negated, and having A, B, and C inputs set to the swapped multiplier, the double-odd multiplicand, and the temporary vector, respectively.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: September 27, 2022
    Assignee: Intel Coporation
    Inventors: Raanan Sade, Thierry Pons, Amit Gradstein, Zeev Sperber, Mark J. Charney, Robert Valentine, Eyal Oz-Sinay
  • Publication number: 20210281851
    Abstract: Systems and methods may provide for occlusion detection in frame rate conversion. Detecting the occlusion allows frame rate conversion to be more accurately performed. In some embodiments, one or more stereoscopic depth cameras may be used to determine the depth of a moving object to more accurately determine the occlusion. In some embodiments, the compression ratio may be adjusted to balance the frame rate and power to help ensure compliance with a power budget. In at least some embodiments, the motion of a camera may be passed from a 3D render pipe to an encoder to avoid motion calculation and thereby saving power.
    Type: Application
    Filed: January 21, 2021
    Publication date: September 9, 2021
    Applicant: Intel Coporation
    Inventors: Jong Dae Oh, Abhishek R. Appu, Stanley J. Baran, Sang-Hee Lee, Atthar H. Mohammed, Hiu-Fai R. Chan, Joydeep Ray
  • Publication number: 20200272883
    Abstract: Techniques and mechanisms to update a synaptic weight of a spiking neural network which is trained to provide a decision of a decision-making sequence. In an embodiment, a synapse of the spiking neural network is associated with a weight which is to be given to communications via that given synapse. The spiking neural network generates output signaling, indicating a decision to the decision-making process, which is evaluated to determine whether, according to predefined test criteria, the decision-making process is successful or unsuccessful. One or more nodes of the spiking neural network receive a reward/penalty signal which is based on the evaluation. In response to the reward/penalty signal indicating a reward event or a penalty event, a synaptic weight value is updated. In another embodiment, input signaling provided to the spiking neural network represents a sub-sequence of two or more most recent states in a sequence of states.
    Type: Application
    Filed: December 19, 2017
    Publication date: August 27, 2020
    Applicant: INTEL COPORATION
    Inventors: Yongqiang CAO, Andreas WILD, Narayan SRINIVASA
  • Patent number: 10528839
    Abstract: Combinatorial shape regression is described as a technique for face alignment and facial landmark detection in images. As described stages of regression may be built for multiple ferns for a facial landmark detection system. In one example a regression is performed on a training set of images using face shapes, using facial component groups, and using individual face point pairs to learn shape increments for each respective image in the set of images. A fern is built based on this regression. Additional regressions are performed for building additional ferns. The ferns are then combined to build the facial landmark detection system.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 7, 2020
    Assignee: INTEL COPORATION
    Inventors: Anbang Yao, Yurong Chen
  • Patent number: 10043740
    Abstract: Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: August 7, 2018
    Assignee: Intel Coporation
    Inventors: Sri Ranga Sai Boyapati, Rahul N. Manepalli, Dilan Seneviratne, Srinivas V. Pietambaram, Kristof Darmawikarta, Robert Alan May, Islam A. Salama
  • Patent number: 9961483
    Abstract: This disclosure describes systems, methods, and devices related to wireless charger cross-talk prevention system. A power transmitting unit (PTU) may determine a power receiving unit (PRU) of one or more PRUs in proximity to a charging area of the PTU. The PTU may detect a communication link between the PTU and the PRU. The PTU may generate an enhanced message, including one or more identifying information associated with the PTU. The PTU may cause to send the enhanced message to the PRU.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 1, 2018
    Assignee: Intel Coporation
    Inventors: Dmitriy Berchanskiy, Nikhil M. Rajpal
  • Publication number: 20170207170
    Abstract: Embodiments herein relate to a system in package (SiP). The SiP may have a first layer of one or more first functional components with respective first active sides and first inactive sides opposite the first active sides. The SiP may further include a second layer of one or more second functional components with respective second active sides and second inactive sides opposite the second active sides. In embodiments, one or more of the first active sides are facing and electrically coupled with one or more of the second active sides through a through-mold via or a through-silicon via.
    Type: Application
    Filed: July 22, 2015
    Publication date: July 20, 2017
    Applicant: INTEL COPORATION
    Inventors: Vijay K. NAIR, Chuan HU, Thorsten MEYER
  • Patent number: 9660085
    Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 23, 2017
    Assignee: Intel Coporation
    Inventors: Han Wui Then, Robert S. Chau, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung, Seung Hoon Hoon Sung, Sanaz K. Gardner, Ravi Pillarisetty
  • Patent number: 9628152
    Abstract: A method for detecting a signal, used in a multi-input multi-output (MIMO) communications system, including: receiving a vector associated with data bits transmitted from the MIMO communications system; finding a first layer from the received vector according to a determining condition, wherein the received vector includes multiple layers, and the multiple layers include the first layer and remaining layers; performing a first scanning procedure for the multiple layers of the received vector to obtain log likelihood ratios (LLR) corresponding to the data bits transmitted from the remaining layers; obtaining a received vector of the first layer according to an equivalent received vector of the remaining layers; and performing a second scanning procedure on data bits of the first layer according to the received vector of the first layer to generate an LLR corresponding to the data bits of the first layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: April 18, 2017
    Assignee: Intel Coporation
    Inventors: Jian Gu, Fei-Feng Xu
  • Patent number: 9373306
    Abstract: Techniques are disclosed for direct viewer projection, which involves having each pixel's emitted light aimed at or otherwise provided directly to the target pupil of a viewing person. In one embodiment, the techniques are implemented using steerable, collimated light sources fashioned into an array to effectively provide a display screen. Each steerable, collimated light source of the array corresponds to one pixel of a given image at a given viewing location, such that no one light source shows a whole image; rather, the whole array is used to display an image. The array can be scanned to provide different images to different viewing locations. The content projected to the different locations may be related (e.g., a movie) or unrelated (e.g., two different movies). A specific viewer can be identified and tracked such that the content is only projected to the target viewer's eyes and no one else's.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: June 21, 2016
    Assignee: Intel Coporation
    Inventors: Maynard C. Falconer, Nathan R. Andrysco
  • Patent number: 9066348
    Abstract: A method, apparatus and system for, in a first wireless device, storing network resources in local memory for a second wireless device while the second wireless device is in an idle mode of operation, receiving a request from the second wireless device to exit the idle mode of operation, retrieving the network resources for the second wireless device from the local memory, and executing a network re-entry process using the retrieved network resources. A method, apparatus and system for, in a local memory of an active base station in a wireless network, storing network resources for an idle wireless mobile device in the wireless network, executing a network re-entry process for the idle wireless mobile device by retrieving and using the network resources for the idle wireless device, and signaling backend components of the wireless network to update the activation status of the wireless mobile device, wherein the network re-entry process is to be initiated prior to signaling the backend components.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: June 23, 2015
    Assignee: INTEL COPORATION
    Inventor: Muthaiah Venkatachalam
  • Patent number: 8987794
    Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: March 24, 2015
    Assignee: Intel Coporation
    Inventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Jessica S. Kachian
  • Patent number: 8923570
    Abstract: Embodiments of a system and method for automatic creation of a multimedia presentation or highlight collection from a collection of candidate contents are generally described herein. In some embodiments, each one of a plurality of videos or images in the candidate contents are automatically evaluated for quality, content, metadata, and desirability based on user specified inclusion factors. Inclusion factors may be utilized to generate one or more scores for the candidate contents, which provide for automatic ranking of the candidate contents. Based on scores generated from the selected inclusion factor criteria a highlight collection of images is automatically generated. The highlight collection can be included in a multimedia presentation, in the form of a memory book, slideshow, or digital narrative, and can be automatically generated from the plurality of videos or images.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: December 30, 2014
    Assignee: Intel Coporation
    Inventors: Steven M. Bennett, Scott Robinson, Vishakha Gupta
  • Publication number: 20140010187
    Abstract: Briefly, in accordance with one or more embodiments, a base station schedules resources for one or more machine-to-machine devices in one or more machine-to-machine groups for a periodic duration persistently. The base station allocates resource blocks for the one or more devices within the scheduled resources, and then receives data packets transmitted from the one or more devices in the allocated resource blocks. The base station may pre-allocate a control channel to be used by the one or more devices during an idle mode for a periodic duration. Uplink synchronization may be performed if one or more of the devices wakes from the idle mode, and the base station may receive data from one or more of the devices in the pre-allocated control channel.
    Type: Application
    Filed: December 27, 2011
    Publication date: January 9, 2014
    Applicant: Intel Coporation
    Inventors: Rui Huang, Honggang Li, Shantidev Mohanty
  • Patent number: 7849334
    Abstract: A method which includes initiating a power management policy based on a processing element for a computing platform entering a given power state. The power management policy includes a determination as to whether an input/output (I/O) controller and a memory controller for the computing platform are substantially quiescent. The computing platform may then be transitioned to a low power system state from a run power system state based on a determination that both the I/O controller and the memory controller are substantially quiescent and an indication that the computing platform is capable of entering the low power system state. According to this method, the low power system state includes entering one or more devices responsive to the computing platform in a power level adequate to retain a configuration state that enables the one or more devices to transition back to the run power system state in a manner that is substantially transparent to an operating system for the computing platform.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: December 7, 2010
    Assignee: Intel Coporation
    Inventors: Dale Juenemann, Paul Diefenbaugh
  • Patent number: 6996749
    Abstract: Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: February 7, 2006
    Assignee: Intel Coporation
    Inventors: Kuljit S. Bains, Robert M. Ellis, Chris B. Freeman, John B. Halbert, David Zimmerman
  • Patent number: 6944290
    Abstract: A digit signal processing system may include a near end and a far end connected by a pair of signal transmission paths. A signal processing may be located at the near end through which signal commands are transmitted to the far end. A signal transducing device may be located at the far end to receive the signal commands and to transmit to the near end signals indicating the state of the signal transducing device. A signal canceller may be operatively associated with the signal processor to subtract undesired signals from the received signals. The signal canceller may employ Auxiliary-Vector filtering.
    Type: Grant
    Filed: April 14, 2001
    Date of Patent: September 13, 2005
    Assignee: Intel Coporation
    Inventor: Vladimir N. Georgiev
  • Patent number: 5978946
    Abstract: In one aspect of the present invention, an apparatus is provided for testing a processor running a software program. The apparatus includes a bus having control, data and address lines and a device assigned at least one address. The bus connects the device to the processor. The apparatus includes a multiple input signature register having a plurality of parallel input terminals connected to the data lines. The apparatus includes a control unit having first and second input terminals connected to the address and control lines respectively. The control unit is adapted to enabling the parallel input terminals of the multiple input signature register in response to detecting on the address and control lines at least one preselected triggering event executed by the software program to a preselected address of the device. The apparatus includes a signature comparator adapted to comparing a test signature number from the multiple input signature register to a reference signature number.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: November 2, 1999
    Assignee: Intel Coporation
    Inventor: Wayne Maurice Needham